Use the generic "distro" boot framework to enable automatic DHCP boot.
MMC and USB are not yet implemented, so this is the only boot option.

The fdt and kernel addresses are adopted from downstream; ramdisk and
scriptaddr addresses were chosen arbitrarily.
Signed-off-by: NAndreas Färber <afaerber@suse.de>
Reviewed-by: NAlexander Graf <agraf@suse.de>

Move it from meson-gxbb-common.h to odroid-c2.h to allow new boards not
to implement it.
Signed-off-by: NAndreas Färber <afaerber@suse.de>

We can make the code read more easily here by simply using memset()
always as when we don't have an optimized version of the function we
will still have a version of this function around anyhow.

Cc: Simon Glass <sjg@chromium.org>
Signed-off-by: NTom Rini <trini@konsulko.com>
Reviewed-by: NSimon Glass <sjg@chromium.org>

We have long had available optimized versions of the memset and memcpy
functions that are borrowed from the Linux kernel.  We should use these
in normal conditions as the speed wins in many workflows outweigh the
relatively minor size increase.  However, we have a number of places
where we're simply too close to size limits in SPL and must be able to
make the size vs performance trade-off in those cases.

Cc: Philippe Reynes <tremyfr@yahoo.fr>
Cc: Eric Jarrige <eric.jarrige@armadeus.org>
Cc: Heiko Schocher <hs@denx.de>
Cc: Magnus Lilja <lilja.magnus@gmail.com>
Cc: Lokesh Vutla <lokeshvutla@ti.com>
Cc: Chander Kashyap <k.chander@samsung.com>
Cc: Akshay Saraswat <akshay.s@samsung.com>
Cc: Simon Glass <sjg@chromium.org>
Cc: Stefan Roese <sr@denx.de>
Signed-off-by: NTom Rini <trini@konsulko.com>
Acked-by: NStefan Roese <sr@denx.de>
Reviewed-by: NSimon Glass <sjg@chromium.org>

While moving OMAP related files to mach-omap2 the functionality
relating to generating secure boot files was modified. This change
prevents secure platforms other than AM33xx and OMAP54XX from
correctly building files for all needed media types.

Fixes: 983e3700 ("arm: Introduce arch/arm/mach-omap2 for OMAP2 derivative platforms")
Signed-off-by: NAndrew F. Davis <afd@ti.com>
Acked-by: NLokesh Vutla <lokeshvutla@ti.com>

Signed-off-by: NAndrew F. Davis <afd@ti.com>
Acked-by: NLokesh Vutla <lokeshvutla@ti.com>
Acked-by: NMichal Simek <michal.simek@xilinx.com>

These files are only included for build by the make system
when CONFIG_SPL_{EXT,FAT}_SUPPORT is enabled, remove the unneed
checks for these in the source files.
Signed-off-by: NAndrew F. Davis <afd@ti.com>
Reviewed-by: NTom Rini <trini@konsulko.com>
Reviewed-by: NSimon Glass <sjg@chromium.org>

IEC 80000-13:2008 Quantities and units
Part 13: Information science and technology

defines the prefixes to use for binary multiples.

So instead of writing
Data Size:    6726132 Bytes = 6568.49 kB = 6.41 MB
in dumpimage we should write
Data Size:    6726132 Bytes = 6568.49 KiB = 6.41 MiB.
Signed-off-by: NHeinrich Schuchardt <xypron.glpk@gmx.de>

In a config with one MMC at device id '1' and no MMC at device id '0'
(a BeagleBone Black with no sd inserted for example), the current code
will first test to access the MMC 0 (sd port), seeing that no device is
present it will simply return that no more device are present for this
class.
This patch fixes this by testing all devices for each class.
Signed-off-by: NEmmanuel Vadot <manu@bidouilliste.com>

The current code can loop undefinitly as it doesn't parse
correctly the env data.
Since the env is an hashtable, use the hashtable function for
the API_ENV_ENUM api call.
Signed-off-by: NEmmanuel Vadot <manu@bidouilliste.com>
Reviewed-by: NSimon Glass <sjg@chromium.org>

Signed-off-by: NSébastien Szymanski <sebastien.szymanski@armadeus.com>

Some scripts are calling the same functions, so these changes consolidate
common scripts together to reduce redundancy and shrink size a bit.  This
also keeps the 'bootargs' variable from growing if manually called more
than one time. This also adds NAND booting scripts based on newly consolidated
scripts.
Signed-off-by: NAdam Ford <aford173@gmail.com>

In 35fc84fa, bootm was refactored so plain 'bootm' and
'bootm <subcommand>' shared a common implementation.
The 'bootm ramdisk' command implementation is now part of the common
implementation but not invoke by plain 'bootm' since the original
implementation never did ramdisk relocation.  Instead, ramdisk
relocation happened in image_setup_linux() which is typically called
during the OS portion of 'bootm'.

On ARM, parameters to the Linux kernel can either be passed by FDT or
ATAGS. When using FDT, image_setup_linux() is called which also triggers
ramdisk relocation.  When using ATAGS, image_setup_linux() is _not_
called because it mostly does FDT setup.

Instead of calling image_setup_linux() in both FDT and ATAGS cases,
include BOOTM_STATE_RAMDISK in the requested states during a plain
'bootm' if CONFIG_SYS_BOOT_RAMDISK_HIGH is set and remove the ramdisk
relocation from image_setup_linux().  This causes ramdisk relocation to
happen on any system where CONFIG_SYS_BOOT_RAMDISK_HIGH regardless of
the OS being booted. Also remove IMAGE_ENABLE_RAMDISK_HIGH as it was
only used by the now-removed code from image_setup_linux().
Signed-off-by: NRick Altherr <raltherr@google.com>
Reviewed-by: NSimon Glass <sjg@chromium.org>
Reviewed-by: NJoel Stanley <joel@jms.id.au>

commit: 65f83802 "serial: 16550: Add getfcr accessor"
breaks u-boot commandline working with long commands
sending to the board.

Since the above patch, you have to setup the fcr register.

For board/archs which enable OF_PLATDATA, the new field
fcr in struct ns16550_platdata is not filled with a
default value ...

This leads in not setting up the uarts fifo, which ends
in problems, when you send long commands to u-boots
commandline.

Detected this issue with automated tbot tests on am335x
based shc board.

The error does not popup, if you type commands. You need
to copy&paste a long command to u-boots commandshell
(or send a long command with tbot)

Possible boards/plattforms with problems:
./arch/arm/cpu/arm926ejs/lpc32xx/devices.c
./arch/arm/mach-tegra/board.c
./board/overo/overo.c
./board/quipos/cairo/cairo.c
./board/logicpd/omap3som/omap3logic.c
./board/logicpd/zoom1/zoom1.c
./board/timll/devkit8000/devkit8000.c
./board/lg/sniper/sniper.c
./board/ti/beagle/beagle.c
./drivers/serial/serial_rockchip.c
Signed-off-by: NHeiko Schocher <hs@denx.de>
Signed-off-by: NLadislav Michl <ladis@linux-mips.org>
Tested-by: NAdam Ford <aford173@gmail.com>
Reviewed-by: NTom Rini <trini@konsulko.com>

On LS1012ARDB board, three dual 1:4 mux/demux devices drive the SDHC2
signals to eMMC, SDIO wifi, SPI and Ardiuno shield. Only when we select
eMMC and SDIO wifi, the SDHC2 could be used. Otherwise, the command
inhibit bits of eSDHC2_PRSSTAT register will never release. This would
cause below continious error messages in linux since it uses polling
mode to detect card.
"mmc1: Controller never released inhibit bit(s)."
"mmc1: Controller never released inhibit bit(s)."
"mmc1: Controller never released inhibit bit(s)."
This patch is to define esdhc_status_fixup function for RDB to disable
SDHC2 status if no SDIO wifi or eMMC is selected.
Signed-off-by: NYangbo Lu <yangbo.lu@nxp.com>
Reviewed-by: NYork Sun <york.sun@nxp.com>

The LS1012AQDS board has a hardware issue. When there is no eMMC
adapter card inserted in SDHC2 adapter slot, the command inhibit
bits of eSDHC2_PRSSTAT register will never release. This would cause
below continious error messages in linux since it uses polling mode
to detect card.
"mmc1: Controller never released inhibit bit(s)."
"mmc1: Controller never released inhibit bit(s)."
"mmc1: Controller never released inhibit bit(s)."
This patch is to define esdhc_status_fixup function for QDS to
disable SDHC2 status if no eMMC adapter card is detected.
Signed-off-by: NYangbo Lu <yangbo.lu@nxp.com>
Reviewed-by: NYork Sun <york.sun@nxp.com>

Move fdt fixup of 'status' property into a weak function. This allows
board to define 'status' fdt fixup by themselves.
Signed-off-by: NYangbo Lu <yangbo.lu@nxp.com>
Reviewed-by: NYork Sun <york.sun@nxp.com>

Enable PPA for ls1043ardb NOR boot and ls1046ardb QSPI boot.
Signed-off-by: NHou Zhiqiang <Zhiqiang.Hou@nxp.com>
Reviewed-by: NYork Sun <york.sun@nxp.com>

Signed-off-by: NHou Zhiqiang <Zhiqiang.Hou@nxp.com>
Reviewed-by: NYork Sun <york.sun@nxp.com>

Moved the config FSL_PPA_ARMV8_PSCI from fsl-layerscape's Kconfig to
Kconfig under armv8 and renamed it to SEC_FIRMWARE_ARMV8_PSCI.
Signed-off-by: NHou Zhiqiang <Zhiqiang.Hou@nxp.com>
Reviewed-by: NYork Sun <york.sun@nxp.com>

Signed-off-by: NHou Zhiqiang <Zhiqiang.Hou@nxp.com>
[York S: clean up scripts/config_whitelist.txt]
Reviewed-by: NYork Sun <york.sun@nxp.com>

For 64-bit kernel, there is a warning about x1-x3 nonzero in violation
of boot protocol. To fix this issue, input argument 4 is added for
armv8_switch_to_el2 and armv8_switch_to_el1. The input argument 4 will
be set to the right value, such as zero.
Signed-off-by: NAlison Wang <alison.wang@nxp.com>
Reviewed-by: NAlexander Graf <agraf@suse.de>
Tested-by: NRyan Harkin <ryan.harkin@linaro.org>
Tested-by: NMichal Simek <michal.simek@xilinx.com>
Reviewed-by: NYork Sun <york.sun@nxp.com>

The default MSI node in kernel tree is for LS1043A rev1.0 silicon, if
rev1.1 silicon used, need to fixup the MSI node to match it.
Signed-off-by: NWenbin Song <wenbin.song@nxp.com>
Signed-off-by: NMingkai Hu <mingkai.hu@nxp.com>
Signed-off-by: NHou Zhiqiang <Zhiqiang.Hou@nxp.com>
Reviewed-by: NYork Sun <york.sun@nxp.com>

The LS1043A rev1.1 silicon supports two types of GIC offset: 4K
alignment and 64K alignment. The bit SCFG_GIC400_ALIGN[GIC_ADDR_BIT]
is used to choose which offset will be used.

The LS1043A rev1.0 silicon only supports the CIG offset with 4K
alignment.

If GIC_ADDR_BIT bit is set, 4K alignment is used, or else 64K alignment
is used. 64K alignment is the default setting.

Overriding the weak smp_kick_all_cpus, the new impletment is able to
detect GIC offset.

The default GIC offset in kernel device tree is using 4K alignment, it
need to be fixed if 64K alignment is detected.
Signed-off-by: NWenbin Song <wenbin.song@nxp.com>
Signed-off-by: NMingkai Hu <mingkai.hu@nxp.com>
Signed-off-by: NHou Zhiqiang <Zhiqiang.Hou@nxp.com>
Reviewed-by: NYork Sun <york.sun@nxp.com>

By default the SATA IP on the ls208Xa SoCs does not generating
coherent/snoopable transactions.  This patch enable it in the
sata axicc register.
Signed-off-by: NTang Yuantian <yuantian.tang@nxp.com>
Reviewed-by: NYork Sun <york.sun@nxp.com>

Add the chip power supply voltage initialization on LS1046ARDB.
Add function power_init_board(), and it will initialize the
PMIC and call the chip power initialization function.
Signed-off-by: NHou Zhiqiang <Zhiqiang.Hou@nxp.com>
Reviewed-by: NYork Sun <york.sun@nxp.com>

Set up chip power supply voltage according to voltage ID.
The fuse status register provides the values from on-chip
voltage ID fuses programmed at the factory. These values
define the voltage requirements for the chip.

Main operations:
1. Set up the core voltage
2. Set up the SERDES voltage and reset SERDES lanes
3. Enable/disable DDR controller support 0.9V if needed
Signed-off-by: NHou Zhiqiang <Zhiqiang.Hou@nxp.com>
Reviewed-by: NYork Sun <york.sun@nxp.com>

Signed-off-by: NHou Zhiqiang <Zhiqiang.Hou@nxp.com>
Reviewed-by: NYork Sun <york.sun@nxp.com>

Signed-off-by: NHou Zhiqiang <Zhiqiang.Hou@nxp.com>
Reviewed-by: NJaehoon Chung <jh80.chung@samsung.com>
Reviewed-by: NYork Sun <york.sun@nxp.com>

This patch adds a simple pmic driver for the mc34vr500 pmic which
is used in conjunction with the fsl T1 and LS1 series SoC.
Signed-off-by: NHou Zhiqiang <Zhiqiang.Hou@nxp.com>
Reviewed-by: NJaehoon Chung <jh80.chung@samsung.com>
Reviewed-by: NYork Sun <york.sun@nxp.com>

Without a prompt in Kconfig, SECURE_BOOT cannot be selected by
defconfig. The option was dropped unintentionally when defconfig
files were cleaned up. Three targets were impacted
ls1043ardb_SECURE_BOOT, ls2080ardb_SECURE_BOOT,
ls2080aqds_SECURE_BOOT.
Signed-off-by: NYork Sun <york.sun@nxp.com>
Reviewed-by: NSimon Glass <sjg@chromium.org>

Add secure boot validation of MC, DPC images using
esbc_validate command.
Signed-off-by: NSumit Garg <sumit.garg@nxp.com>
Signed-off-by: NUdit Agarwal <udit.agarwal@nxp.com>
Reviewed-by: NYork Sun <york.sun@nxp.com>

Update bootscript and its hdr addresses for Layerscape Chasis 3
based platforms instead of individual SoCs.
Signed-off-by: NSumit Garg <sumit.garg@nxp.com>
Signed-off-by: NUdit Agarwal <udit.agarwal@nxp.com>
Reviewed-by: NYork Sun <york.sun@nxp.com>

Enable driver model for eSDHC on ls1012a rdb and qds boards.
Signed-off-by: NYangbo Lu <yangbo.lu@nxp.com>
Reviewed-by: NYork Sun <york.sun@nxp.com>

This patch is to add eSDHC nodes for ls1012a.
Signed-off-by: NYangbo Lu <yangbo.lu@nxp.com>
Reviewed-by: NYork Sun <york.sun@nxp.com>

This patch is to add 'fsl,esdhc' into of_match table to support
driver model for QorIQ eSDHC.
Signed-off-by: NYangbo Lu <yangbo.lu@nxp.com>
Reviewed-by: NYork Sun <york.sun@nxp.com>

There would be compiling error as below when enable driver model for esdhc.
undefined reference to `dm_gpio_get_value'
undefined reference to `gpio_request_by_name_nodev'
This patch is to make GPIO support optional with CONFIG_DM_GPIO. Because
all boards of QorIQ platform don't need it and they just check register for
CD/WP status, only some boards of i.MX platform require this.
Signed-off-by: NYangbo Lu <yangbo.lu@nxp.com>
Acked-by: NJaehoon Chung <jh80.chung@samsung.com>
Reviewed-by: NYork Sun <york.sun@nxp.com>

This patch binds the sys_info->freq_systembus to Platform PLL, and
implements the IPs' clock function individually.
Signed-off-by: NHou Zhiqiang <Zhiqiang.Hou@nxp.com>
Reviewed-by: NYork Sun <york.sun@nxp.com>

Up to now, there are 3 kind of SoCs under Layerscape Chassis 2,
like LS1043A, LS1046A and LS1012A. But the clocks tree has a
lot of differences, for instance, the IP modules have different
dividers to derive its clock from Platform PLL. And the core
cluster PLL and platform PLL maybe have different reference
clocks, such as LS1012A. Another problem is which clock/PLL
should be described by sys_info->freq_systembus, it is confused
in Layerscape Chissis 2.

This patch is to bind the sys_info->freq_systembus to the Platform
PLL, and handle the different divider of IP modules separately
between different SoCs, and separate reference clocks of core
cluster PLL and platform PLL.
Signed-off-by: NHou Zhiqiang <Zhiqiang.Hou@nxp.com>
Reviewed-by: NYork Sun <york.sun@nxp.com>