- 26 8月, 2019 9 次提交
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由 Tom Rini 提交于
- Migrate SYS_SPI_U_BOOT_OFFS, SYS_NAND_USE_FLASH_BBT and ARCH_CPU_INIT to Kconfig
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由 Hannes Schmelzer 提交于
This converts the following to Kconfig: CONFIG_SYS_SPI_U_BOOT_OFFS Signed-off-by: NHannes Schmelzer <hannes.schmelzer@br-automation.com> [trini: Expose this for SPL_SPI_SUNXI for now] Signed-off-by: NTom Rini <trini@konsulko.com>
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由 Hannes Schmelzer 提交于
the x530 board needs conversion of SPL_SPI_LOAD to Kconfig first Signed-off-by: NHannes Schmelzer <hannes.schmelzer@br-automation.com> Reviewed-by: NChris Packham <chris.packham@alliedtelesis.co.nz>
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由 Hannes Schmelzer 提交于
Exact two boards are referencing CONFIG_SYS_SPI_U_BOOT_OFFS to another define, we replace this manually with the value for having a clean run of moveconfig.py afterwards. Signed-off-by: NHannes Schmelzer <hannes.schmelzer@br-automation.com>
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由 Hannes Schmelzer 提交于
some boards have common headers for several individual build-targets where CONFIG_SYS_SPI_U_BOOT_OFFS is defined even it is not needed (only needed if CONFIG_SPL_SPI_LOAD is defined also). Take this define here under '#ifdef CONFIG_SPL_SPI_LOAD' for having a clean run of moveconfig.py Signed-off-by: NHannes Schmelzer <hannes.schmelzer@br-automation.com>
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由 Hannes Schmelzer 提交于
Some boards have coded this offset with formula or bitshifts in their board-config. Manually convert these things into hex-values to be able using moveconfig.py afterwards. Signed-off-by: NHannes Schmelzer <hannes.schmelzer@br-automation.com>
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由 Stefan Roese 提交于
Convert CONFIG_SYS_NAND_USE_FLASH_BBT to Kconfig, update defconfigs, headers and whitelist. Please note that this symbol already was used in Kconfig (imply in CONFIG_NAND_ATMEL) which did not work, since this symbol was not available in Kconfig. This changes now with this patch and all boards with CONFIG_NAND_ATMEL will have BBT enabled. Which is what I also need on my GARDENA AT91SAM based board. Signed-off-by: NStefan Roese <sr@denx.de> Cc: Eugen Hristev <eugen.hristev@microchip.com> Cc: Miquel Raynal <miquel.raynal@bootlin.com> Cc: Gregory CLEMENT <gregory.clement@bootlin.com> [trini: Rework such that the configs are unchanged to start with] Signed-off-by: NTom Rini <trini@konsulko.com>
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由 Adam Ford 提交于
This converts the following to Kconfig: CONFIG_ARCH_CPU_INIT Signed-off-by: NAdam Ford <aford173@gmail.com> Acked-by: NChris Packham <chris.packham@alliedtelesis.co.nz> Tested-by: NFelix Brack <fb@ltec.ch>
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由 Tom Rini 提交于
Rsync all defconfig files using moveconfig.py Signed-off-by: NTom Rini <trini@konsulko.com>
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- 24 8月, 2019 6 次提交
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https://gitlab.denx.de/u-boot/custodians/u-boot-rockchip由 Tom Rini 提交于
- remove rk3288 fennec board - remove SPL raw image support for Rockchip SoCs - add common misc_init_r() for ethaddr from cpuid - enable USB HOST support for rk3328 - unify code for finding a valid gpt in part driver
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由 Tom Rini 提交于
- Migrate CONFIG_MX_CYCLIC, CONFIG_FSL_USDHC and CONFIG_MXS_GPIO to Kconfig - Fix some SPL/TPL and ARM64 dependencies
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由 Adam Ford 提交于
This converts the following to Kconfig: CONFIG_MX_CYCLIC Signed-off-by: NAdam Ford <aford173@gmail.com> Acked-by: NDavid Lechner <david@lechnology.com>
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由 Adam Ford 提交于
This converts the following to Kconfig: CONFIG_FSL_USDHC Signed-off-by: NAdam Ford <aford173@gmail.com> [trini: Add IMX8M, TARGET_S32V234EVB to FSL_USDHC list] Signed-off-by: NTom Rini <trini@konsulko.com>
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由 Adam Ford 提交于
Several options are presenting themselves on a various boards where the options are clearly not used. (ie, arm64 options on arm9, or SPL/TPL options when SPL or TPL are not defined) This patch is not attempting to be a complete list of items, but more like low hanging fruit. This patch attempts to reduce some of the menuconfig noise by defining dependencies so they don't appear when not used. Signed-off-by: NAdam Ford <aford173@gmail.com>
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由 Lukasz Majewski 提交于
This converts the following to Kconfig: CONFIG_MXS_GPIO Travis-CI: https://travis-ci.org/lmajewski/u-boot-dfu/builds/571260789Signed-off-by: NLukasz Majewski <lukma@denx.de> Acked-by: NPeng Fan <peng.fan@nxp.com> Acked-by: NJagan Teki <jagan@amarulasolutions.com>
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- 23 8月, 2019 17 次提交
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由 Max Kellermann 提交于
This was changed to 1 in commit 0717dde0, but a few months later, commit 5f9411af swapped the order of eMMC and SD card by assigning indexed aliases to `&sdhci` and `&sdmmc`. Signed-off-by: NMax Kellermann <max.kellermann@gmail.com> Reviewed-by: NKever Yang <kever.yang@rock-chips.com> (Add signature) Signed-off-by: NKever Yang <kever.yang@rock-chips.com>
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由 Urja Rannikko 提交于
Some ChromeOS devices (atleast veyron speedy) have the first 8MiB of the eMMC write protected and equipped with a dummy 'IGNOREME' GPT header - instead of spewing error messages about it, just silently try the backup GPT. Note: this does not touch the gpt cmd writing/verifying functions, those will still complain. Signed-off-by: NUrja Rannikko <urjaman@gmail.com> Reviewed-by: NKever Yang <kever.yang@rock-chips.com>
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由 Urja Rannikko 提交于
There were 3 copies of the same sequence, make it into a function. Signed-off-by: NUrja Rannikko <urjaman@gmail.com> Reviewed-by: NKever Yang <kever.yang@rock-chips.com>
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由 Rohan Garg 提交于
We should use the shared helpers to setup the necessary parts Signed-off-by: NRohan Garg <rohan.garg@collabora.com> Reviewed-by: NKever Yang <kever.yang@rock-chips.com>
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由 Rohan Garg 提交于
This enables us to set a static MAC address Signed-off-by: NRohan Garg <rohan.garg@collabora.com> Reviewed-by: NKever Yang <kever.yang@rock-chips.com>
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由 Rohan Garg 提交于
Generate a MAC address based on the cpuid available in the efuse block: Use the first 6 byte of the cpuid's SHA256 hash and set the locally administered bits. Also ensure that the multicast bit is cleared. The MAC address is only generated and set if there is no ethaddr present in the saved environment. This is based off of Klaus Goger's work in 8adc9d Signed-off-by: NRohan Garg <rohan.garg@collabora.com> Reviewed-by: NKever Yang <kever.yang@rock-chips.com>
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由 Kever Yang 提交于
Since there is no one using this board, remove it. Signed-off-by: NKever Yang <kever.yang@rock-chips.com>
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由 Kever Yang 提交于
RK3399 SPL only support FIT image for ATF bl31. Signed-off-by: NKever Yang <kever.yang@rock-chips.com>
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由 Kever Yang 提交于
RK3368 SPL only support FIT image for ATF bl31. Signed-off-by: NKever Yang <kever.yang@rock-chips.com>
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由 Kever Yang 提交于
RK3328 SPL only support FIT image for ATF bl31. Signed-off-by: NKever Yang <kever.yang@rock-chips.com>
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由 Kever Yang 提交于
Use Kconfig for option SYS_MALLOC_LEN and default to 0x2000000. Signed-off-by: NKever Yang <kever.yang@rock-chips.com>
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由 Kever Yang 提交于
According to rock64 schemetic, both VCC_HOST1_5V and VCC_HOST_5V are controlled by USB20_HOST_DRV(GPIO0A2), fix it so that we can get correct power supply for USB HOST ports. Signed-off-by: NKever Yang <kever.yang@rock-chips.com>
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由 Kever Yang 提交于
Move all the nodes only shown in u-boot to -u-boot.dtsi to make rk3328.dtsi clean. Signed-off-by: NKever Yang <kever.yang@rock-chips.com>
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由 Kever Yang 提交于
Rock64 has a USB3.0 port, enable the controller so that we can use it. Signed-off-by: NKever Yang <kever.yang@rock-chips.com>
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由 Kever Yang 提交于
Required to successfully probe the ehci generic driver Signed-off-by: NKever Yang <kever.yang@rock-chips.com>
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由 Kever Yang 提交于
We need to store all the ram related cap/map info back to register for each channel after all the init has been done in case some of register was reset during the process. Signed-off-by: NYouMin Chen <cym@rock-chips.com> Signed-off-by: NKever Yang <kever.yang@rock-chips.com>
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- 22 8月, 2019 8 次提交
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https://gitlab.denx.de/u-boot/custodians/u-boot-fsl-qoriq由 Tom Rini 提交于
- i2c dm model support of lx2160a, ls1088a, lx2088a, ls1028a - icid setup for ls1028a, ls1088a - other small fixes
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由 Laurentiu Tudor 提交于
Add ICID setup for the platform devices contained on this chip: usb, sata, sdhc, edma, qdma, gpu, display and sec. Signed-off-by: NLaurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: NHoria Geantă <horia.geanta@nxp.com> Reviewed-by: NPrabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
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由 Laurentiu Tudor 提交于
Add ICID setup for the platform devices contained on this chip: usb, sata, sdhc, sec. The ICID macros for SEC needed to be adapted because the format of the registers is different. Signed-off-by: NLaurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: NHoria Geantă <horia.geanta@nxp.com> Reviewed-by: NPrabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
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由 Laurentiu Tudor 提交于
The current implementation assumes that the registers holding the ICIDs are universally big endian. That's no longer the case on newer platforms so update the code to take into account the endianness of each register. Signed-off-by: NLaurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: NHoria Geantă <horia.geanta@nxp.com> Reviewed-by: NPrabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
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由 Laurentiu Tudor 提交于
Add CCSR base addresses for ESDHC2, EDMA QDMA, DISPLAY and GPU devices. Signed-off-by: NLaurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: NPrabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
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由 Laurentiu Tudor 提交于
Add defines for all the SEC job rings base addresses. Signed-off-by: NLaurentiu Tudor <laurentiu.tudor@nxp.com> Reviewed-by: NHoria Geantă <horia.geanta@nxp.com> Reviewed-by: NPrabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
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由 Chuanhua Han 提交于
By default, i2c input clock is platform clk / 2, but some of the platform of i2c clock divider does not meet this kind of circumstance, so alone to set default values for these platforms. Signed-off-by: NChuanhua Han <chuanhua.han@nxp.com> Reviewed-by: NPrabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
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由 Chuanhua Han 提交于
BRDCFG4[USBOSC] and BRDCFG5[SPR] register field of Qixis device is used to control SPI and other IP signal routing. USBOSC: 0= SPI_CLK used as external USB REFCLK input driven with 24.000 MHz. SPI devices are unusable in this mode. 1= SPI_CLK used as SPI clock. SPI devices are usable in this mode. USB block is clocked from internal sources SPR[3:2]: SPI_CS / SDHC_DAT4:7 Routing (schematic net CFG_SPI_ROUTE[3:2]): 00= SDHC/eMMC 8-bit 01= SD Card Rev 2.0/3.0 10= SPI on-board memory 11= TDM Riser / SPI off-board connector. The default value is 00 if an SDCard/eMMC card is selected as the boot device. SPR[1:0]: SPI_SIN/SOUT/SCK Routing (schematic net CFG_SPI_ROUTE[1:0]): 00= SDHC Sync loop 01= TDM Riser / SPI off-board connector. 10= SPI on-board memory. 11= SPI off-board connector. By default, the SPI feature is not available, so we need to configure the above register fields to select the route to the SPI feature. Signed-off-by: NChuanhua Han <chuanhua.han@nxp.com> Reviewed-by: NPrabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
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