- 10 12月, 2015 10 次提交
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由 Hans de Goede 提交于
Select SYS_NS16550 from Kconfig instead of setting it in all our defconfig files. Signed-off-by: NHans de Goede <hdegoede@redhat.com>
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由 vishnupatekar 提交于
Add dts and defconfig for h8homletv2 board. H8Homlet Proto v2.0 Board is A83T Dev Board by Allwinner. It has UART, ethernet, USB, HDMI, etc ports on it. A83T patches are tested on this board. Signed-off-by: NVishnu Patekar <vishnupatekar0510@gmail.com> Reviewed-by: NHans de Goede <hdegoede@redhat.com> Signed-off-by: NHans de Goede <hdegoede@redhat.com>
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由 vishnupatekar 提交于
Allwinner A83T is new octa-core cortex-a7 SOC. This adds the basic dtsi, the clocks differs from earlier sun8i SOCs. This is not yet included in kernel. Signed-off-by: NVishnu Patekar <vishnupatekar0510@gmail.com> Reviewed-by: NHans de Goede <hdegoede@redhat.com> Signed-off-by: NHans de Goede <hdegoede@redhat.com>
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由 vishnupatekar 提交于
Add support for A83T dram. Register are different from sun8i A33. init code is similar to A33 dram init. hope we'll shift duplicate code in dram_sun8i_* to dram helper in future. Signed-off-by: NVishnu Patekar <vishnupatekar0510@gmail.com> Reviewed-by: NHans de Goede <hdegoede@redhat.com> Signed-off-by: NHans de Goede <hdegoede@redhat.com>
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由 vishnupatekar 提交于
Add basic clocks pll1, pll5, and some default values from allwinner u-boot. Signed-off-by: NVishnu Patekar <vishnupatekar0510@gmail.com> [hdegoede@redhat.com] Fix PLL6 init to run at 600 MHz instead of 288 MHz, fixing the mmc support not working [hdegoede@redhat.com] Fix PLL init code to properly wait for the PLL-s to stabilize, fixing cold-booting directly from sdcard not working Signed-off-by: NHans de Goede <hdegoede@redhat.com>
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由 vishnupatekar 提交于
Enabled support for AXP818 in SPL and u-boot. DCDC1, DCDC2, DCDC3 and DCSC5 are enabled. Signed-off-by: NVishnu Patekar <vishnupatekar0510@gmail.com> Reviewed-by: NHans de Goede <hdegoede@redhat.com> Signed-off-by: NHans de Goede <hdegoede@redhat.com>
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由 vishnupatekar 提交于
AXP818 is rsb based PMIC and used on Allwinner A83T H8 Homlet dev board. It's registers are different and calculating reg config is different than that of earlier axp power ICs. DCDC1, DCDC2, DCDC3 and DCDC5 is implemented at the moment. all other voltages can be added subsequently. AXP datasheet is uploaded to wiki: http://linux-sunxi.org/File:AXP818_datasheet_Revision1.0.pdfSigned-off-by: NVishnu Patekar <vishnupatekar0510@gmail.com> Reviewed-by: NHans de Goede <hdegoede@redhat.com> Signed-off-by: NHans de Goede <hdegoede@redhat.com>
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由 vishnupatekar 提交于
On A83T, PB9,PB10 are UART0 pins. On allwinner A83T Dev board(h8homlet), this uart0 serial connector is exposed. Signed-off-by: NVishnu Patekar <vishnupatekar0510@gmail.com> Reviewed-by: NHans de Goede <hdegoede@redhat.com> Signed-off-by: NHans de Goede <hdegoede@redhat.com>
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由 vishnupatekar 提交于
Allwinner A83T is octa-core cortex-a7 SOC. This enables support for A83T. SMP is not yet supported. Signed-off-by: NVishnu Patekar <vishnupatekar0510@gmail.com> Reviewed-by: NHans de Goede <hdegoede@redhat.com> Signed-off-by: NHans de Goede <hdegoede@redhat.com>
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由 Hans de Goede 提交于
According to the datasheets the max speed of AHB1 is 276 MHz, so setting it to PLL6 / 3 which gives us 200MHz everywhere is fine, and gives us a nice speed-up in certain workloads. Suggested-by: NChen-Yu Tsai <wens@csie.org> Signed-off-by: NHans de Goede <hdegoede@redhat.com> Acked-by: NIan Campbell <ijc@hellion.org.uk> Tested-by: NChen-Yu Tsai <wens@csie.org>
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- 09 12月, 2015 8 次提交
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由 Bin Meng 提交于
These are currently dead codes. Until we have complete ACPI support, we don't know if it works or not. Remove to avoid confusion. Signed-off-by: NBin Meng <bmeng.cn@gmail.com> Acked-by: NSimon Glass <sjg@chromium.org> Tested-by: NSimon Glass <sjg@chromium.org>
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由 Bin Meng 提交于
This Kconfig option name indicates it has something to do with cpu socket, however it is actually not the case. Remove it and move options inside it to NORTHBRIDGE_INTEL_IVYBRIDGE. Signed-off-by: NBin Meng <bmeng.cn@gmail.com> Acked-by: NSimon Glass <sjg@chromium.org> Tested-by: NSimon Glass <sjg@chromium.org>
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由 Bin Meng 提交于
There are some options which are never used, and also some options which are selected by others but have never been a Kconfg option. Clean these up. Signed-off-by: NBin Meng <bmeng.cn@gmail.com> Acked-by: NSimon Glass <sjg@chromium.org> Tested-by: NSimon Glass <sjg@chromium.org>
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由 Bin Meng 提交于
NORTHBRIDGE_INTEL_SANDYBRIDGE is for sandybridge, not ivybridge. Signed-off-by: NBin Meng <bmeng.cn@gmail.com> Acked-by: NSimon Glass <sjg@chromium.org> Tested-by: NSimon Glass <sjg@chromium.org>
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由 Bin Meng 提交于
With driver model timer support, there should not be an explict call to timer_init(). Remove this call for x86. Signed-off-by: NBin Meng <bmeng.cn@gmail.com> Acked-by: NSimon Glass <sjg@chromium.org>
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由 Bin Meng 提交于
Right now i8254_init() is called from timer_init() in the tsc timer driver. But actually i8254 and tsc are completely different things. Since tsc timer has been converted to driver model, we should find a new place that is appropriate for U-Boot to call i8254_init(), which is now x86_cpu_init_f(). Signed-off-by: NBin Meng <bmeng.cn@gmail.com> Acked-by: NSimon Glass <sjg@chromium.org>
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由 Bin Meng 提交于
With recent ns16550 driver changes, we only changed the legacy UART (at I/O port 0x3f8) compatible string, but forgot to change the PCI UART compatible string. Now fix it. Signed-off-by: NBin Meng <bmeng.cn@gmail.com> Acked-by: NSimon Glass <sjg@chromium.org>
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由 Bin Meng 提交于
Currently OF_BAD_ADDR is always -1ULL. When using OF_BAD_ADDR as the return value of dev_get_addr(), it creates potential size mismatch as dev_get_addr() uses FDT_ADDR_T_NONE as the return value which can be either -1U or -1ULL depending on CONFIG_PHYS_64BIT. Now we change OF_BAD_ADDR to FDT_ADDR_T_NONE to avoid such case. Signed-off-by: NBin Meng <bmeng.cn@gmail.com> Acked-by: NSimon Glass <sjg@chromium.org> Reviewed-by: NStefan Roese <sr@denx.de>
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- 08 12月, 2015 3 次提交
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由 Alexey Brodkin 提交于
This commit adds support of USB 2.0 storage media on AXS10x boards. Signed-off-by: NAlexey Brodkin <abrodkin@synopsys.com> Cc: Marek Vasut <marex@denx.de> Cc: Simon Glass <sjg@chromium.org>
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由 Tom Rini 提交于
Signed-off-by: NTom Rini <trini@konsulko.com>
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由 Marek Vasut 提交于
Seems 6ae6e160 broke creating images in certain cases, there are two problems with that patch. First is that the expression "!x == 4 || !x == 6" is ambiguous. The intention here was "!(x == 4) || !(x == 6)" based on reading further in the file, where this was borrowed from. This however is interpreted by gcc as "(!x) == 4 || (!x) == 6" and always false. gcc-5.x will warn about this case. The second problem is that we do not want to test for the case of "(NOT x is 4) OR (NOT x is 6)" but instead "(x is not equal to 4) AND (x is not equal to 6)". This is because in those two cases we already execute the code question in another part of the file. Rewrite the expression and add parenthesis for clarity. Signed-off-by: NMarek Vasut <marex@denx.de> Cc: Tom Rini <trini@konsulko.com> Cc: Philippe De Swert <philippedeswert@gmail.com> Cc: Simon Glass <sjg@chromium.org> [trini: Re-word Marek's explanation]
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- 07 12月, 2015 19 次提交
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由 Tom Rini 提交于
Now that we may compile (but not link) code calling fixup_cmdtable when this is not set, we need to always have the declaration available. We should also make sure that anyone calling the function includes <command.h> as that's where the function declaration is. Signed-off-by: NTom Rini <trini@konsulko.com>
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由 Michal Simek 提交于
This option is needed for all SoCs which have nodes on bus. Without enabling this drivers are not found and probed. Issue was found on Zynq MMC probe. Enable this option by default. Signed-off-by: NMichal Simek <michal.simek@xilinx.com> Reviewed-by: NStefan Roese <sr@denx.de> Reviewed-by: NSimon Glass <sjg@chromium.org>
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由 Michal Simek 提交于
Subcommands contain pointers to functions which are not updated when MANUAL_RELOC is enabled. This patch fix it. Signed-off-by: NMichal Simek <michal.simek@xilinx.com> Reviewed-by: NSimon Glass <sjg@chromium.org>
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由 Michal Simek 提交于
Subcommands contain pointers to functions which are not updated when MANUAL_RELOC is enabled. This patch fix it. Signed-off-by: NMichal Simek <michal.simek@xilinx.com> Acked-by: NHeiko Schocher <hs@denx.de> Reviewed-by: NSimon Glass <sjg@chromium.org>
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由 Michal Simek 提交于
debug_uart.h is included twice. Signed-off-by: NMichal Simek <michal.simek@xilinx.com> Reviewed-by: NBin Meng <bmeng.cn@gmail.com> Reviewed-by: NSimon Glass <sjg@chromium.org>
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由 Michal Simek 提交于
Remove this c&p error from s5p driver. Signed-off-by: NMichal Simek <michal.simek@xilinx.com> Reviewed-by: NBin Meng <bmeng.cn@gmail.com> Reviewed-by: NSimon Glass <sjg@chromium.org>
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由 Michal Simek 提交于
Move driver to DM Signed-off-by: NMichal Simek <michal.simek@xilinx.com> Reviewed-by: NSimon Glass <sjg@chromium.org>
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由 Michal Simek 提交于
Prepare for using DM. Signed-off-by: NMichal Simek <michal.simek@xilinx.com>
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Calculate the minimum sd clock based on max clock. This will be done by add_sdhci() if we pass minimum clock as zero. It also does based on SD host contoller version. Signed-off-by: NSiva Durga Prasad Paladugu <sivadur@xilinx.com> Signed-off-by: NMichal Simek <michal.simek@xilinx.com>
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由 Michal Simek 提交于
Remove unused macros when driver was moved to DM. Signed-off-by: NMichal Simek <michal.simek@xilinx.com>
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由 Michal Simek 提交于
SPL DM MMC FAT requires more malloc space(3k fat buffers + dm) that it is available now. Extend SPL malloc space. Current OCM layout: 0xffff0000 - 0xfff2000 - Full malloc space 0xffff2000 - 0xffff300 - Stack location 0xfffff300 - CONFIG_SYS_MALLOC_F_LEN - Early malloc space 0xfffffd00 - sizeof(GD) - GD 0xfffffe00 - 0xffffffff - SoC specific boot code Signed-off-by: NMichal Simek <michal.simek@xilinx.com>
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由 Michal Simek 提交于
The patch "board_init: Change the logic to setup malloc_base" (sha1: 9ac4fc82) breaks SPL for Zynq because it puts early alloc area on the stack which caused that stack was decreased by CONFIG_SYS_MALLOC_F_LEN (0x400) and there was not enough space for regular stack. This patch changes memory layout to better utilize the last 64k OCM block. 0xffff0000 - 0xfff1000 - Full malloc space 0xffff1000 - 0xffff300 - Stack location 0xfffff300 - CONFIG_SYS_MALLOC_F_LEN - Early malloc space 0xfffffd00 - sizeof(GD) - GD 0xfffffe00 - 0xffffffff - SoC specific boot code Signed-off-by: NMichal Simek <michal.simek@xilinx.com> Tested-by: NMoritz Fischer <moritz.fischer@ettus.com>
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由 Michal Simek 提交于
Signed-off-by: NMichal Simek <michal.simek@xilinx.com>
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由 Michal Simek 提交于
Remove configuration options from board file. Signed-off-by: NMichal Simek <michal.simek@xilinx.com>
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由 Michal Simek 提交于
Enable to break waiting loop at any time. Signed-off-by: NMichal Simek <michal.simek@xilinx.com> Acked-by: NJoe Hershberger <joe.hershberger@ni.com>
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由 Michal Simek 提交于
Signed-off-by: NMichal Simek <michal.simek@xilinx.com> Reviewed-by: NJagan Teki <jteki@openedev.com>
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由 Michal Simek 提交于
Do not set interface via configs. Read information from DT. Signed-off-by: NMichal Simek <michal.simek@xilinx.com> Reviewed-by: NJagan Teki <jteki@openedev.com>
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由 Michal Simek 提交于
- Enable DM_ETH by default for Zynq and ZynqMP - Remove board_eth_init code - Change miiphy_read function to return value instead of error code based on DM requirement - Do not enable EMIO DT support by default Signed-off-by: NMichal Simek <michal.simek@xilinx.com> Reviewed-by: NJagan Teki <jteki@openedev.com> Reviewed-by: NSimon Glass <sjg@chromium.org> Reviewed-by: NBin Meng <bmeng.cn@gmail.com>
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