The NAND configuration has had the ethernet missing, so this patch
enables the on-board ethernet interface.
Signed-off-by: NAdam Ford <aford173@gmail.com>

Several options are presenting themselves on a various boards
where the options are clearly not used.  (ie, SPL/TPL options
when SPL or TPL are not defined)

This patch is not attempting to be a complete list of items, but
more like low hanging fruit.  In some instances, I wasn't sure
of DM was required, so I simply made them SPL or TPL.

This patch attempts to reduce some of the menuconfig noise
by defining dependencies so they don't appear when not used.
Signed-off-by: NAdam Ford <aford173@gmail.com>

Signed-off-by: NSamuel Egli <samuel.egli@siemens.com>
Acked-by: NRoger Meier <r.meier@siemens.com>
Cc: Heiko Schocher <hs@denx.de>

Update my email address from gmail to my domain.
Signed-off-by: NRicardo Ribalda Delgado <ricardo@ribalda.com>

To address the following warning message:

===================== WARNING ======================
This board does not use CONFIG_DM_USB. Please update
the board to use CONFIG_DM_USB before the v2019.07 release.
Failure to update by the deadline may result in board removal.
See doc/driver-model/MIGRATION.txt for more info.
====================================================

CONFIG_DM_USB is enabled, this resulted in SPL build errors:

drivers/built-in.o: In function 'xhci_dwc3_probe':
u-boot/drivers/usb/host/xhci-dwc3.c:155: undefined reference to 'usb_get_dr_mode'
scripts/Makefile.spl:404: recipe for target 'spl/u-boot-spl' failed
make[1]: *** [spl/u-boot-spl] Error 1
Makefile:1721: recipe for target 'spl/u-boot-spl' failed
make: *** [spl/u-boot-spl] Error 2

Enabling usb common library and usb ethernet drivers in SPL
does the job. Target was compile tested, build was clean.
Signed-off-by: NSuniel Mahesh <sunil.m@techveda.org>

When large writes take place I saw a Samsung EVO 970+ return a status
value of 0x13, PRP Offset Invalid.  I tracked this down to the
improper handling of PRP entries.  The blocks the PRP entries are
placed in cannot cross a page boundary and thus should be allocated
on page boundaries.  This is how the Linux kernel driver works.

With this patch, the PRP pool is allocated on a page boundary and
other than the very first allocation, the pool size is a multiple of
the page size.  Each page can hold (4096 / 8) - 1 entries since the
last entry must point to the next page in the pool.
Signed-off-by: NAaron Williams <awilliams@marvell.com>
Reviewed-by: NBin Meng <bmeng.cn@gmail.com>

The command "pci bar" and "pci region" display the address and size in
16 characters including "0x", so the command can only display
14 hexadecimal digits if the number of digits in the address and size is
less than 14.

    ID   Base                Size                Width  Type
    ----------------------------------------------------------
     0   0x00000020000000  0x00000000100000  64     MEM   Prefetchable
     1   0xffff000080000000  0x00000000100000  64     MEM   Prefetchable

The 64-bit address and size should be displayed in 18(= 16+2) digits,
so this patch adjusts them.

Cc: Yehuda Yitschak <yehuday@marvell.com>
Cc: Simon Glass <sjg@chromium.org>
Signed-off-by: NKunihiko Hayashi <hayashi.kunihiko@socionext.com>
Reviewed-by: NBin Meng <bmeng.cn@gmail.com>

Some of the USB code is still being built into SPL even when the
SPL menu options have it explicitly disabled for SPL. Unit there is
a better solution, This patch undefines CONFIG_USB_EHCI_OMAP when
building SPL which reduces the code and lets the board boot again.

Fixes: 25e4ff45 ("ARM: omap3_logic: Enable OMAP EHCI support
for SOM-LV Boards")
Signed-off-by: NAdam Ford <aford173@gmail.com>

The assigned value NULL is overwritten before being used. Remove the
assignment.
Signed-off-by: NHeinrich Schuchardt <xypron.glpk@gmx.de>
Reviewed-by: NBin Meng <bmeng.cn@gmail.com>

To support KVM, we need to drop at EL2 and not EL1 before we boot Linux
kernel. This causes issues on platform with VHE and secondaries booting
at EL2 via TF-A PSCI CPU_ON call.

Cc: Ryan Harkin <ryan.harkin@linaro.org>
Cc: Liviu Dudau <liviu.dudau@foss.arm.com>
Cc: Linus Walleij <linus.walleij@linaro.org>
Cc: David Feng <fenghua@phytium.com.cn>
Signed-off-by: NSudeep Holla <sudeep.holla@arm.com>
Reviewed-by: NPeng Fan <peng.fan@nxp.com>

earlyprintk no longer works on arm64 platforms. Replace it with earlycon
which works fine.

Cc: Ryan Harkin <ryan.harkin@linaro.org>
Cc: Liviu Dudau <liviu.dudau@foss.arm.com>
Cc: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: NSudeep Holla <sudeep.holla@arm.com>
Reviewed-by: NPeng Fan <peng.fan@nxp.com>
Reviewed-by: NRyan Harkin <ryan.harkin@linaro.org>
Reviewed-by: NLinus Walleij <linus.walleij@linaro.org>

File was found on specified location. Info about file was read,
but then immediately destroyed using 'free' call. As a result
file size was set to 0, hence fat process didn't read any data.

Premature 'free' call removed. Resources are freed right before
function return. File is read correctly.
Signed-off-by: NMartin Vystrcil <martin.vystrcil@m-linux.cz>

The scsi_scan_dev() is looping over the number of uc_plat->max_id.
The number of actual ports a AHCI controller has can be greater than
max_id. Update uc_plat->max_id to make SCSI scan all detected ports.
Signed-off-by: NAiden Park <aiden.park@intel.com>
Reviewed-by: NBin Meng <bmeng.cn@gmail.com>

When the pinmux configuration was added, it was accidentally placed into
the omap3_pmx_wkup node  when it should have been placed into the
omap3_pmx_core.  This error was accidentally propagated to U-Boot by
me when I blindly copied the device tree from Linux.

This patch moves the i2c2_pins and i2c3_pins to the correct node
which should eliminate i2c bus errors and timeouts due to the fact
the bootloader uses the save device tree that no longer properly
assigns these pins.
Signed-off-by: NAdam Ford <aford173@gmail.com>

Noncached area at present is being initialized to random space after malloc
area. It works in most the cases as it goes to stack area & stack is not
overwriting it being far from it.
Signed-off-by: NVikas Manocha <vikas.manocha@st.com>

When devnum was changed to a local variable in distro_bootcmd we ran
into a problem on TI platforms (confirmed on Beaglebone) as we had been
using 'setenv devnum' there as well and it needs to match the other
usage.

Fixes: 13dd6665 ("distro: not taint environment variables if possible")
[trini: Review other platforms, re-word commit message]
Signed-off-by: NTom Rini <trini@konsulko.com>

- Migrate SYS_SPI_U_BOOT_OFFS, SYS_NAND_USE_FLASH_BBT and ARCH_CPU_INIT
  to Kconfig

This converts the following to Kconfig:
   CONFIG_SYS_SPI_U_BOOT_OFFS
Signed-off-by: NHannes Schmelzer <hannes.schmelzer@br-automation.com>
[trini: Expose this for SPL_SPI_SUNXI for now]
Signed-off-by: NTom Rini <trini@konsulko.com>

the x530 board needs conversion of SPL_SPI_LOAD to Kconfig first
Signed-off-by: NHannes Schmelzer <hannes.schmelzer@br-automation.com>
Reviewed-by: NChris Packham <chris.packham@alliedtelesis.co.nz>

Exact two boards are referencing CONFIG_SYS_SPI_U_BOOT_OFFS to another
define, we replace this manually with the value for having a clean run
of moveconfig.py afterwards.
Signed-off-by: NHannes Schmelzer <hannes.schmelzer@br-automation.com>

some boards have common headers for several individual build-targets
where CONFIG_SYS_SPI_U_BOOT_OFFS is defined even it is not needed (only
needed if CONFIG_SPL_SPI_LOAD is defined also). Take this define here
under '#ifdef CONFIG_SPL_SPI_LOAD' for having a clean run of
moveconfig.py
Signed-off-by: NHannes Schmelzer <hannes.schmelzer@br-automation.com>

Some boards have coded this offset with formula or bitshifts in their
board-config. Manually convert these things into hex-values to be able
using moveconfig.py afterwards.
Signed-off-by: NHannes Schmelzer <hannes.schmelzer@br-automation.com>

Convert CONFIG_SYS_NAND_USE_FLASH_BBT to Kconfig, update defconfigs,
headers and whitelist.

Please note that this symbol already was used in Kconfig
(imply in CONFIG_NAND_ATMEL) which did not work, since this symbol was
not available in Kconfig. This changes now with this patch and all
boards with CONFIG_NAND_ATMEL will have BBT enabled. Which is what
I also need on my GARDENA AT91SAM based board.
Signed-off-by: NStefan Roese <sr@denx.de>
Cc: Eugen Hristev <eugen.hristev@microchip.com>
Cc: Miquel Raynal <miquel.raynal@bootlin.com>
Cc: Gregory CLEMENT <gregory.clement@bootlin.com>
[trini: Rework such that the configs are unchanged to start with]
Signed-off-by: NTom Rini <trini@konsulko.com>

This converts the following to Kconfig:
   CONFIG_ARCH_CPU_INIT
Signed-off-by: NAdam Ford <aford173@gmail.com>
Acked-by: NChris Packham <chris.packham@alliedtelesis.co.nz>
Tested-by: NFelix Brack <fb@ltec.ch>

Rsync all defconfig files using moveconfig.py
Signed-off-by: NTom Rini <trini@konsulko.com>

- remove rk3288 fennec board
- remove SPL raw image support for Rockchip SoCs
- add common misc_init_r() for ethaddr from cpuid
- enable USB HOST support for rk3328
- unify code for finding a valid gpt in part driver

- Migrate CONFIG_MX_CYCLIC, CONFIG_FSL_USDHC and CONFIG_MXS_GPIO to
  Kconfig
- Fix some SPL/TPL and ARM64 dependencies

This converts the following to Kconfig:
   CONFIG_MX_CYCLIC
Signed-off-by: NAdam Ford <aford173@gmail.com>
Acked-by: NDavid Lechner <david@lechnology.com>

This converts the following to Kconfig:
   CONFIG_FSL_USDHC
Signed-off-by: NAdam Ford <aford173@gmail.com>
[trini: Add IMX8M, TARGET_S32V234EVB to FSL_USDHC list]
Signed-off-by: NTom Rini <trini@konsulko.com>

Several options are presenting themselves on a various boards
where the options are clearly not used.  (ie, arm64 options on
arm9, or SPL/TPL options when SPL or TPL are not defined)

This patch is not attempting to be a complete list of items, but
more like low hanging fruit.

This patch attempts to reduce some of the menuconfig noise
by defining dependencies so they don't appear when not used.
Signed-off-by: NAdam Ford <aford173@gmail.com>

This converts the following to Kconfig:
   CONFIG_MXS_GPIO

Travis-CI: https://travis-ci.org/lmajewski/u-boot-dfu/builds/571260789Signed-off-by: NLukasz Majewski <lukma@denx.de>
Acked-by: NPeng Fan <peng.fan@nxp.com>
Acked-by: NJagan Teki <jagan@amarulasolutions.com>

This was changed to 1 in commit 0717dde0, but a few months later,
commit 5f9411af swapped the order of eMMC and SD card by assigning
indexed aliases to `&sdhci` and `&sdmmc`.
Signed-off-by: NMax Kellermann <max.kellermann@gmail.com>
Reviewed-by: NKever Yang <kever.yang@rock-chips.com>
(Add signature)
Signed-off-by: NKever Yang <kever.yang@rock-chips.com>

Some ChromeOS devices (atleast veyron speedy) have the first 8MiB of
the eMMC write protected and equipped with a dummy 'IGNOREME' GPT
header - instead of spewing error messages about it, just silently
try the backup GPT.

Note: this does not touch the gpt cmd writing/verifying functions,
those will still complain.
Signed-off-by: NUrja Rannikko <urjaman@gmail.com>
Reviewed-by: NKever Yang <kever.yang@rock-chips.com>

There were 3 copies of the same sequence, make it into a function.
Signed-off-by: NUrja Rannikko <urjaman@gmail.com>
Reviewed-by: NKever Yang <kever.yang@rock-chips.com>

We should use the shared helpers to setup the necessary parts
Signed-off-by: NRohan Garg <rohan.garg@collabora.com>
Reviewed-by: NKever Yang <kever.yang@rock-chips.com>

This enables us to set a static MAC address
Signed-off-by: NRohan Garg <rohan.garg@collabora.com>
Reviewed-by: NKever Yang <kever.yang@rock-chips.com>

Generate a MAC address based on the cpuid available in the efuse
block: Use the first 6 byte of the cpuid's SHA256 hash and set the
locally administered bits. Also ensure that the multicast bit is
cleared.

The MAC address is only generated and set if there is no ethaddr
present in the saved environment.

This is based off of Klaus Goger's work in 8adc9d
Signed-off-by: NRohan Garg <rohan.garg@collabora.com>
Reviewed-by: NKever Yang <kever.yang@rock-chips.com>

Since there is no one using this board, remove it.
Signed-off-by: NKever Yang <kever.yang@rock-chips.com>

RK3399 SPL only support FIT image for ATF bl31.
Signed-off-by: NKever Yang <kever.yang@rock-chips.com>