- 27 9月, 2017 11 次提交
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由 Philipp Tomsich 提交于
Update the generic EHCI driver to support a live tree. Signed-off-by: NPhilipp Tomsich <philipp.tomsich@theobroma-systems.com>
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由 Philipp Tomsich 提交于
Update the DWC2 USB driver to support a live tree. Signed-off-by: NPhilipp Tomsich <philipp.tomsich@theobroma-systems.com>
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由 Philipp Tomsich 提交于
Update the Rockchip xhci wrapper driver to support a live device tree. Signed-off-by: NPhilipp Tomsich <philipp.tomsich@theobroma-systems.com>
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由 Bin Meng 提交于
When EHCD and xHCD are enabled at the same time, USB storage device driver will fail to read/write from/to the storage device attached to the xHCI interface, due to its transfer blocks exceeds the xHCD driver limitation. With driver model, we have an API to get the controller's maximum transfer size and we can use that to determine the storage driver's capability of read/write. Note: the non-DM version driver is still broken with xHCD and the intent here is not to fix the non-DM one, since the xHCD itself is already broken in places like 3.0 hub support, etc. Signed-off-by: NBin Meng <bmeng.cn@gmail.com>
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由 Bin Meng 提交于
This adds a new memeber max_xfer_blk in struct us_data to record the maximum number of transfer blocks for the storage device. It is set per HCD setting, and so far is to 65535 for EHCD and 20 for everything else. Signed-off-by: NBin Meng <bmeng.cn@gmail.com>
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由 Bin Meng 提交于
EHCD can handle any transfer length as long as there is enough free heap space left, hence set the theoretical max number SIZE_MAX. Signed-off-by: NBin Meng <bmeng.cn@gmail.com>
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由 Bin Meng 提交于
xHCD allocates one segment which includes 64 TRBs for each endpoint and the last TRB in this segment is configured as a link TRB to form a TRB ring. Each TRB can transfer up to 64K bytes, however data buffers referenced by transfer TRBs shall not span 64KB boundaries. Hence the maximum number of TRBs we can use in one transfer is 62. Signed-off-by: NBin Meng <bmeng.cn@gmail.com>
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由 Bin Meng 提交于
The HCD may have limitation on the maximum bytes to be transferred in a USB transfer. USB class driver needs to be aware of this. Signed-off-by: NBin Meng <bmeng.cn@gmail.com>
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由 Marek Vasut 提交于
The Linux kernel driver sets the number of event segments and entries to 1 , while the initial import of the xhci code set that values to 3 for reasons unknown. While most controllers are fine with more event segments with more entries, there are standard-conformant controllers (ie. Renesas RCar xHCI) which only support 1 event segment. Set the number of event segments and event entries back to 1 to allow such controllers to work with U-Boot xHCI stack. Note that the Renesas controller correctly indicates ERST Max = 1 in HCSPARAMS2[7:4] . Signed-off-by: NMarek Vasut <marek.vasut+renesas@gmail.com> Cc: Bin Meng <bmeng.cn@gmail.com>
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由 Heinrich Schuchardt 提交于
memset(newpart, '\0', sizeof(newpart)); only initializes the firest 4 or 8 bytes of *newpart and not the whole structure disk_part. We should use sizeof(struct disk_part). Instead of malloc and memset we can use calloc. Identified by cppcheck. Fixes: 09a49930 GPT: read partition table from device into a data structure Reported-by: Coverity (CID: 167228) Cc: Stefan Roese <sr@denx.de> Signed-off-by: NHeinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: NStefan Roese <sr@denx.de> Reviewed-by: NSimon Glass <sjg@chromium.org>
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- 26 9月, 2017 13 次提交
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由 Marek Vasut 提交于
The status register is optional in the AMD command sets, but it's presence can be checked by reading out CFI table entry 0xc bit 0. If the register is present, prefer using it's bit 7 to determine if the flash is busy over reading the flash ; this is needed ie. on Hyperflash memories. Signed-off-by: NMarek Vasut <marek.vasut+renesas@gmail.com> Signed-off-by: NStefan Roese <sr@denx.de>
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由 Marek Vasut 提交于
Embed the flash base into struct flash_info instead of having ad-hoc static array in the code. This does not only remove static variable, but also allows CFI-like controllers, ie. HyperFlash ones, to use most of the CFI flash code by populating the flash_info with matching base address. Signed-off-by: NMarek Vasut <marek.vasut+renesas@gmail.com> Signed-off-by: NStefan Roese <sr@denx.de>
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由 Baruch Siach 提交于
Signed-off-by: NBaruch Siach <baruch@tkos.co.il> Signed-off-by: NStefan Roese <sr@denx.de>
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由 Baruch Siach 提交于
The ClearFog Base boot from UART when setting the DIP switches to 01001. Unfortunately, the SPL code sometimes fails to detect the UART boot method at run-time. Add an alternative SAR UART boot value to fix this. Note that this alternative value is not documented (Armada 38x Hardware Specifications, Table 48). But experimentations showed it on the ClearFog Base. Signed-off-by: NBaruch Siach <baruch@tkos.co.il> Signed-off-by: NStefan Roese <sr@denx.de>
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由 Chris Packham 提交于
dram_ecc_scrubbing() had code to skip unused DRAM banks but it would not work because mvebu_sdram_bs() returns 0 and the code was subtracting 1 before checking the size. Remove the -1 from the bank size and the +1 from the total which will skip unused banks and still calculate the correct size. Put the -1 where it is needed for scrubbing via the xor engine. Reported-by: NJoshua Scott <joshua.scott@alliedtelesis.co.nz> Signed-off-by: NChris Packham <judge.packham@gmail.com> Signed-off-by: NStefan Roese <sr@denx.de>
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由 Chris Packham 提交于
The Armada-38x has 1.8GHz and 2.0GHz variants. Add entries for these variants to the sar_freq_tab. Signed-off-by: NChris Packham <judge.packham@gmail.com> Signed-off-by: NStefan Roese <sr@denx.de>
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由 Joshua Scott 提交于
Display more information about the current RAM configuration. With these changes the output on a 88F6820 board is SoC: MV88F6820-A0 at 1600 MHz DRAM: 2 GiB (800 MHz, 32-bit, ECC not enabled) Signed-off-by: NJoshua Scott <joshua.scott@alliedtelesis.co.nz> Signed-off-by: NChris Packham <judge.packham@gmail.com> Reviewed-by: NStefan Roese <sr@denx.de> Signed-off-by: NStefan Roese <sr@denx.de>
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由 Chris Packham 提交于
These SoCs are network packet processors (switch chips) with integrated ARMv7 cores. They share a great deal of commonality with the Armada-XP CPUs. Signed-off-by: NChris Packham <judge.packham@gmail.com> Reviewed-by: NStefan Roese <sr@denx.de> Signed-off-by: NStefan Roese <sr@denx.de>
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由 Stefan Roese 提交于
Currently, we support 2 "theadorable" MVEBU build targets. One with a stripped down configuration (theadorable) and one with a full blown configuration (theadorable_debug), including PCI, ethernet etc. When we introduced these configs, the plan was to remove the debug version at some point. But now it seems better to keep the full-blown version and remove the "non-debug" version instead. At a later stage, I will rename the remaining "theadorable_debug" target into a more fitting one. Signed-off-by: NStefan Roese <sr@denx.de>
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由 Chris Packham 提交于
This converts the following to Kconfig: CONFIG_MVNETA Signed-off-by: NChris Packham <judge.packham@gmail.com> Reviewed-by: NSimon Glass <sjg@chromium.org> Signed-off-by: NStefan Roese <sr@denx.de>
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- 25 9月, 2017 6 次提交
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由 Suresh Gupta 提交于
In some of the QSPI controller version, there must be atleast 128bit data available in TX FIFO for any pop operation otherwise error bit will be set. The code will not make any behavior change for previous controller as the transfer data size in ipcr register is still the same. Patch is tested on LS1046A which do not require 16 bytes aligned and LS1088A which require 16 bytes aligned data in TX FIFO Signed-off-by: NSuresh Gupta <suresh.gupta@nxp.com> Signed-off-by: NAnupam Kumar <anupam.kumar_1@nxp.com> Reviewed-by: NJagan Teki <jagan@openedev.com>
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由 Vsevolod Gribov 提交于
Spansion S25FS256S and S25FL256S flashes have equal JEDEC ID and ext ID. As far as S25FL256S occures in spi_flash_ids before S25FS256S, U-Boot incorrectly detects FS flash as FL. Thus its better to compare with S25FS256S first. Signed-off-by: NVsevolod Gribov <vgribov@larch-networks.com> [Added S-o-b] Signed-off-by: NJagan Teki <jagan@openedev.com> Reviewed-by: NJagan Teki <jagan@openedev.com>
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由 Marek Vasut 提交于
The flash chip is 2 MiB , organized as 32 x 64 kiB sectors . Rectify the entry to match the datasheet, reality and Linux SNOR IDs. Signed-off-by: NMarek Vasut <marex@denx.de> Reviewed-by: NJagan Teki <jagan@openedev.com>
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由 Yogesh Gaur 提交于
Add MT35XU512ABA1G12 parameters to NOR flash parameters array. The MT35XU512ABA1G12 only supports 1 bit mode and 8 bits. It can't support dual and quad. Supports subsector erase with 4KB granularity, have support of FSR(flag status register) and flash size is 64MB. Signed-off-by: NYogesh Gaur <yogeshnarayan.gaur@nxp.com> Reviewed-by: NJagan Teki <jagan@openedev.com>
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由 Suresh Gupta 提交于
It is recommended to check either controller is free to take new spi action. The IP_ACC and AHB_ACC bits indicates that the controller is busy in IP or AHB mode respectively. And the BUSY bit indicates that controller is currently busy handling a transaction to an external flash device Signed-off-by: NSuresh Gupta <suresh.gupta@nxp.com> Reviewed-by: NJagan Teki <jagan@openedev.com>
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由 Peng Fan 提交于
Add driver model support for mxc spi driver. Most functions are restructured to be reused by DM and non-DM. Tested on mx6slevk/mx6qsabresd board. Signed-off-by: NPeng Fan <peng.fan@nxp.com> Reviewed-by: NJagan Teki <jagan@openedev.com> Reviewed-by: NStefano Babic <sbabic@denx.de>
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- 24 9月, 2017 6 次提交
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由 Tom Rini 提交于
In some cases, such as FreeBSD, the path to an alternative dtc needs to be used. Rather than override the one given in the Makefile on the command line, make this part of the build configuration. Signed-off-by: NTom Rini <trini@konsulko.com>
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由 Tom Rini 提交于
This makes us act like the Linux Kernel does and allow for dtc to be provided externally but otherwise we use the version of dtc that is included in the sources. This in turn means that we can drop the checkdtc logic. We select DTC in the cases where we will need the dtc tool provided. Signed-off-by: NTom Rini <trini@konsulko.com>
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由 Tom Rini 提交于
This adds the following commits from upstream: fe50bd1ecc1d fdtget: Split out cell list display into a new function 62d812308d11 README: Add a note about test_tree1.dts 5bed86aee9e8 pylibfdt: Add support for fdt_subnode_offset() 46f31b65b3b3 pylibfdt: Add support for fdt_node_offset_by_phandle() a3ae43723687 pylibfdt: Add support for fdt_parent_offset() a198af80344c pylibfdt: Add support for fdt_get_phandle() b9eba92ea50f tests: Return a failure code when any tests fail 155faf6cc209 pylibfdt: Use local pylibfdt module 50e5cd07f325 pylibfdt: Add a test for use of uint32_t ab78860f09f5 pylibfdt: Add stdint include to fix uint32_t 36f511fb1113 tests: Add stacked overlay tests on fdtoverlay 1bb00655d3e5 fdt: Allow stacked overlays phandle references a33c2247ac8d Introduce fdt_setprop_placeholder() method 0016f8c2aa32 dtc: change default phandles to ePAPR style instead of both e3b9a9588a35 tests: fdtoverlay unit test 42409146f2db fdtoverlay: A tool that applies overlays aae22722fc8d manual: Document missing options 13ce6e1c2fc4 dtc: fix sprintf() format string error, again d990b8013889 Makefile: Fix build on MSYS2 and Cygwin 51f56dedf8ea Clean up shared library compile/link options 21a2bc896e3d Suppress expected error message in fdtdump test 2a42b14d0d03 dtc: check.c fix compile error a10cb3c818d3 Fix get_node_by_path string equality check 548aea2c436a fdtdump: Discourage use of fdtdump c2258841a785 fdtdump: Fix over-zealous version check 9067ee4be0e6 Fix a few whitespace and style nits e56f2b07be38 pylibfdt: Use setup.py to build the swig file 896f1c133265 pylibfdt: Use Makefile constructs to implement NO_PYTHON 90db6d9989ca pylibfdt: Allow setup.py to operate stand-alone e20d9658cd8f Add Coverity Scan support b04a2cf08862 pylibfdt: Fix code style in setup.py 1c5170d3a466 pylibfdt: Rename libfdt.swig to libfdt.i 580a9f6c2880 Add a libfdt function to write a property placeholder ab15256d8d02 pylibfdt: Use the call function to simplify the Makefile 9f2e3a3a1f19 pylibfdt: Use the correct libfdt version in the module e91c652af215 pylibfdt: Enable installation of Python module 8a892fd85d94 pylibfdt: Allow building to be disabled 741cdff85d3e .travis.yml: Add builds with and without Python library prerequisites 14c4171f4f9a pylibfdt: Use package_dir to set the package directory 89a5062ab231 pylibfdt: Use environment to pass C flags and files 4e0e0d049757 pylibfdt: Allow pkg-config to be supplied in the environment 6afd7d9688f5 Correct typo: s/pylibgfdt/pylibfdt/ 756ffc4f52f6 Build pylibfdt as part of the normal build process 8cb3896358e9 Adjust libfdt.h to work with swig b40aa8359aff Mention pylibfdt in the documentation 12cfb740cc76 Add tests for pylibfdt 50f250701631 Add an initial Python library for libfdt cdbb2b6c7a3a checks: Warn on node name unit-addresses with '0x' or leading 0s 4c15d5da17cc checks: Add bus checks for simple-bus buses 33c3985226d3 checks: Add bus checks for PCI buses Signed-off-by: NTom Rini <trini@konsulko.com>
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由 Tom Rini 提交于
This adds the following commits from upstream: 558cd81bdd43 dtc: Bump version to v1.4.4 c17a811c62eb fdtput: Remove star from value_len documentation 194d5caaefcb fdtget: Use @return to document the return value d922ecdd017b tests: Make realloc_fdt() really allocate *fdt 921cc17fec29 libfdt: overlay: Check the value of the right variable 9ffdf60bf463 dtc: Simplify asm_emit_string() implementation 881012e44386 libfdt: Change names of sparse helper macros bad5b28049e5 Fix assorted sparse warnings 672ac09ea04d Clean up gcc attributes 49300f2ade6a dtc: Don't abuse struct fdt_reserve_entry Signed-off-by: NTom Rini <trini@konsulko.com>
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由 Tom Rini 提交于
Using the update-dtc-source.sh script from Linux v4.14-rc1 import the portions of dtc that we require. We bring in update-dtc-source.sh and scripts/dtc/Makefile from Linux v4.14-rc1. Rework DTC_FLAGS handling to not require a test. Signed-off-by: NTom Rini <trini@konsulko.com>
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- 23 9月, 2017 4 次提交
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由 Frank Kunz 提交于
For EFI boot GPT partition table support is needed as well as the part command and also the SPL needs to fallback to other boot methods after parse the SPL header. Signed-off-by: NFrank Kunz <mailinglists@kunz-im-inter.net>
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由 Masahiro Yamada 提交于
GCC 7.1 warns: duplicate ‘const’ declaration specifier [-Wduplicate-decl-specifier] Signed-off-by: NMasahiro Yamada <yamada.masahiro@socionext.com>
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由 Masahiro Yamada 提交于
CONFIG_NAND_DENALI select's CONFIG_SYS_NAND_SELF_INIT, so the NAND initialization process is driven by the driver itself. CONFIG_SYS_NAND_MAX_CHIPS and CONFIG_SYS_NAND_BASE are unused. Signed-off-by: NMasahiro Yamada <yamada.masahiro@socionext.com>
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