- 17 9月, 2020 4 次提交
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由 Heiko Schocher 提交于
add DM/DTS support for the UEC ethernet on QUICC Engine Block. Signed-off-by: NHeiko Schocher <hs@denx.de> Patch-cc: Mario Six <mario.six@gdsys.cc> Patch-cc: Qiang Zhao <qiang.zhao@nxp.com> Patch-cc: Holger Brunck <holger.brunck@hitachi-powergrids.com> Patch-cc: Madalin Bucur <madalin.bucur@oss.nxp.com> Series-changes: 3 - revert: commit "3374264d" ("drivers: net: qe: deselect QE when DM_ETH is enabled") as now qe works with DM and DM_ETH support. - fix mailaddress from Holger Series-changes: 2 - add comments from Qiang Zhao: - add device node documentation - I did not drop the dm_qe_uec_phy.c and use drivers/net/fsl_mdio.c because using drivers/net/fsl_mdio.c leads in none existent udevice mdio@3320 instead boards with DM ETH support should use now this driver. - remove RFC tag Commit-notes: - I let the old none DM based implementation in code so boards should work with old implementation. This Code should be removed if all boards are converted to DM/DTS. - add the DM based qe uec driver under drivers/net/qe - Therefore copied the files uccf.c uccf.h uec.h from drivers/qe. So there are a lot of Codingstyle problems currently. I fix them in next version if this RFC patch is OK or it needs some changes. - The dm based driver code is now under drivers/net/qe/dm_qe_uec.c Used a lot of functions from drivers/qe/uec.c - seperated the PHY specific code into seperate file drivers/net/qe/dm_qe_uec_phy.c END
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由 Heiko Schocher 提交于
add DM support for parallel I/O ports on QUICC Engine Block Signed-off-by: NHeiko Schocher <hs@denx.de> Patch-cc: Mario Six <mario.six@gdsys.cc> Patch-cc: Qiang Zhao <qiang.zhao@nxp.com> Patch-cc: Holger Brunck <holger.brunck@hitachi-powergrids.com> Series-changes: 2 - remove RFC - fixed Codingstyle errors, therefore new patch powerpc, mpc83xx: fix codingstyle issues for qe_io.c - moved DM part to drivers/pinctrl Commit-notes: Open questions / discussion: - I let the old none DM based implementation in code so boards should work with old implementation. This should be removed if all boards are converted to DM/DTS. - Unfortunately linux DTS does not use "pinctrl-" properties, instead "pio-handle" properties. Even worser old U-Boot code initializes all pins defined in "const qe_iop_conf_t qe_iop_conf_tab[]" table in board code. As linux does the same I decided to also scan through all subnodes containing "pio-map" property and initialize them too. The proper solution would be to check for "pio-handle" when a device is probed. END
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由 Heiko Schocher 提交于
fix Codingstyle for files in drivers/qe, remaining following check warnings: $ ./scripts/checkpatch.pl -f drivers/qe/uec.h CHECK: Macro argument reuse '_bd' - possible side-effects? +#define BD_ADVANCE(_bd, _status, _base) \ + (((_status) & BD_WRAP) ? (_bd) = \ + ((struct buffer_descriptor *)(_base)) : ++(_bd)) total: 0 errors, 0 warnings, 1 checks, 692 lines checked $ ./scripts/checkpatch.pl -f drivers/qe/uec_phy.h total: 0 errors, 0 warnings, 0 checks, 214 lines checked $ ./scripts/checkpatch.pl -f drivers/qe/uccf.c total: 0 errors, 0 warnings, 0 checks, 507 lines checked $ ./scripts/checkpatch.pl -f drivers/qe/uec.c total: 0 errors, 0 warnings, 0 checks, 1434 lines checked $ ./scripts/checkpatch.pl -f drivers/qe/uec_phy.c total: 0 errors, 0 warnings, 0 checks, 927 lines checked $ ./scripts/checkpatch.pl -f drivers/qe/qe.c CHECK: Lines should not end with a '(' +U_BOOT_CMD( total: 0 errors, 0 warnings, 1 checks, 830 lines checked Signed-off-by: NHeiko Schocher <hs@denx.de>
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由 Heiko Schocher 提交于
remove extern void qe_init(uint qe_base); extern void qe_reset(void); and include fsl_qe.h instead. Signed-off-by: NHeiko Schocher <hs@denx.de> Series-changes: 2 - new in v2
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- 16 9月, 2020 1 次提交
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https://gitlab.denx.de/u-boot/custodians/u-boot-ti由 Tom Rini 提交于
- Hyperflash boot for J7200 - Update Main R5FSS lockstep mode - R5F remoteproc support for J7200 - Minor env fixes - Add SPI boot support for am335x-icev2
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- 15 9月, 2020 26 次提交
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由 Faiz Abbas 提交于
am335x internal SRAM is too small to support the addition of SPI bootmode to the default defconfig. Add a separate spiboot_defconfig Signed-off-by: NFaiz Abbas <faiz_abbas@ti.com>
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由 Faiz Abbas 提交于
Add an ofdata_to_platdata() callback to access dts in U-boot and access all platform data in it. This prepares the driver for supporting both device tree as well as static platform data structures in SPL. Signed-off-by: NFaiz Abbas <faiz_abbas@ti.com>
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由 Faiz Abbas 提交于
Add platform data and a device structure for the spi device present on am335x-icev2. This requires moving all omap3_spi platform data structures and symbols to an omap3_spi.h so that the board file can access them. Signed-off-by: NFaiz Abbas <faiz_abbas@ti.com>
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由 Faiz Abbas 提交于
There are devices which don't use OF_CONTROL or OF_PLATDATA but instead rely on statically defined platdata. Block dm_scan_fdt_dev() with both configs to avoid build failures under this condition. Signed-off-by: NFaiz Abbas <faiz_abbas@ti.com> Reviewed-by: NJagan Teki <jagan@amarulasolutions.com>
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由 Faiz Abbas 提交于
Add spi and spi nor flash nodes for am335x-icev2. Signed-off-by: NFaiz Abbas <faiz_abbas@ti.com>
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由 Matwey V. Kornilov 提交于
Signed-off-by: NMatwey V. Kornilov <matwey.kornilov@gmail.com>
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由 Matwey V. Kornilov 提交于
If devtype variable is setted via setenv, then the following devtype=X style is ignored. Currently, many u-boot commands use devtype variable in the latter manner: mmc_boot=if mmc dev ${devnum}; then devtype=mmc; run scan_dev_for_boot_part; fi Use devtype=mmc instead of setenv devtype mmc to avoid bugs with booting from another devtype. Signed-off-by: NMatwey V. Kornilov <matwey.kornilov@gmail.com>
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由 Suman Anna 提交于
Enable the FS_LOADER and associated configs in the j7200_evm_r5_defconfig so that the R5 SPL can support the loading of firmware files from a boot media/file system. Signed-off-by: NSuman Anna <s-anna@ti.com>
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由 Suman Anna 提交于
Add a generic fs_loader node to the K3 J7200 R5 common board dts file and use it as the chosen firmware-loader so that it can be used for loading various firmwares from a boot media/filesystem in R5 SPL on K3 J7200 EVM. Signed-off-by: NSuman Anna <s-anna@ti.com>
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由 Suman Anna 提交于
The R5 SPL on J7200 SoCs will be limited to booting just the MCU R5FSS0 R5F core in LockStep-mode at present, so add the two required environment variables 'addr_mcur5f0_0load' and 'name_mcur5f0_0fw' that are needed by the R5 SPL early-boot logic. The firmware name used is also different from that on J721E SoCs. Signed-off-by: NSuman Anna <s-anna@ti.com>
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由 Suman Anna 提交于
The A72 U-boot can support early booting of any of the Main or MCU R5F remote processors from U-boot prompt to achieve various system usecases before booting the Linux kernel. Update the default BOOTCOMMAND to provide an automatic and easier way to start various remote processors through added environment variables. Signed-off-by: NSuman Anna <s-anna@ti.com>
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由 Suman Anna 提交于
The J7200 SoCs has two R5F sub-systems. Enable the TI K3 R5F remoteproc driver and the remoteproc command options to allow these R5F processors to be booted from A72 U-Boot. The Kconfigs are added using savedefconfig. Signed-off-by: NSuman Anna <s-anna@ti.com>
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由 Suman Anna 提交于
The J7200 SoCs have different number of remote processors, but reuse the same environment settings as the J721E SoCs. The current env variable rproc_fw_binaries is geared towards J721E SoCs and is incorrect for J7200 SoCs. Please see the logic originally added in commit 0b4ab9c9 ("env: ti: j721e-evm: Add support to boot rprocs including R5Fs and DSPs"). Fix this by defining the DEFAULT_RPROCS macro appropriately using the corresponding TARGET_EVM Kconfig symbol. This macro is used by the 'rproc_fw_binaries' env variable in the common remoteproc env header file k3_rproc.h. The list of R5F cores to be started before loading and booting the Linux kernel are as follows, and mainly comprises of the Main R5FSS0 cores in this order: Main R5FSS0 (Split) Core0 : 2 /lib/firmware/j7200-main-r5f0_0-fw Main R5FSS0 (Split) Core1 : 3 /lib/firmware/j7200-main-r5f0_1-fw The MCU R5FSS0 is in LockStep mode and is expected to be booted by R5 SPL, so it is not included in the list. The order of rprocs to boot cannot be really modified as only the Main R5FSS0 cores are involved and Core0 has to be booted first always before the corresponding Core1. Signed-off-by: NSuman Anna <s-anna@ti.com>
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由 Suman Anna 提交于
The J7200 SoCs have 2 dual-core Arm Cortex-R5F processor (R5FSS) subsystems/clusters. One R5F cluster is present within the MCU domain (MCU_R5FSS0), and the other one is present within the MAIN domain (MAIN_R5FSS0). Each of these can be configured at boot time to be either run in a LockStep mode or in an Asymmetric Multi Processing (AMP) fashion in Split-mode. These subsystems have 64 KB each Tightly-Coupled Memory (TCM) internal memories for each core split between two banks - ATCM and BTCM (further interleaved into two banks). The TCMs of both Cores are combined in LockStep-mode to provide a larger 128 KB of memory. Add the DT node for the MAIN domain R5F cluster/subsystem, the two R5F cores are added as child nodes to the main cluster/subsystem node. The cluster is configured to run in Split-mode by default, with the ATCMs enabled to allow the R5 cores to execute code from DDR with boot-strapping code from ATCM. The inter-processor communication between the main A72 cores and these processors is achieved through shared memory and Mailboxes. Signed-off-by: NSuman Anna <s-anna@ti.com>
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由 Suman Anna 提交于
The J7200 SoCs have 2 dual-core Arm Cortex-R5F processor (R5FSS) subsystems/clusters. One R5F cluster is present within the MCU domain (MCU_R5FSS0), and the other one is present within the MAIN domain (MAIN_R5FSS0). Each of these can be configured at boot time to be either run in a LockStep mode or in an Asymmetric Multi Processing (AMP) fashion in Split-mode. These subsystems have 64 KB each Tightly-Coupled Memory (TCM) internal memories for each core split between two banks - ATCM and BTCM (further interleaved into two banks). The TCMs of both Cores are combined in LockStep-mode to provide a larger 128 KB of memory. Add the DT node for the MCU domain R5F cluster/subsystem, the two R5F cores are added as child nodes to the main cluster/subsystem node. The cluster is configured to run in LockStep mode by default, with the ATCMs enabled to allow the R5 cores to execute code from DDR with boot-strapping code from ATCM. The inter-processor communication between the main A72 cores and these processors is achieved through shared memory and Mailboxes. Signed-off-by: NSuman Anna <s-anna@ti.com>
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由 Suman Anna 提交于
The A72 U-Boot code can load and boot a number of the available R5FSS Cores on the J7200 SoC. Change the memory attributes for the DDR regions used by the remote processors so that the cores can see and execute the proper code. The J7200 SoC has less number of remote processors compared to J721E, so use less memory for the remote processors. So, a separate table based on the current J721E table is added for J7200 SoCs, and selected using the appropriate Kconfig CONFIG_TARGET_J7200_A72_EVM symbol. Signed-off-by: NSuman Anna <s-anna@ti.com>
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由 Suman Anna 提交于
The K3 J7200 SoC family has a revised R5F sub-system and contains a subset of the R5F clusters present on J721E SoCs. The integration of these clusters is very much similar to J721E SoCs otherwise. The revised IP has the following two new features: 1. TCMs are auto-initialized during module power-up, and the behavior is programmable through a MMR bit controlled by System Firmware. 2. The LockStep-mode allows the Core1 TCMs to be combined with the Core0 TCMs effectively doubling the amount of TCMs available. The LockStep-mode on previous SoCs could only use the Core0 TCMs. This combined TCMs appear contiguous at the respective Core0 TCM addresses. Add the support to these clusters in the K3 R5F remoteproc driver using J7200 specific compatibles and revised logic accounting for the above IP features/differences. Signed-off-by: NSuman Anna <s-anna@ti.com>
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由 Suman Anna 提交于
The K3 J7200 SoCs have two dual-core Arm R5F clusters/subsystems, with 2 R5F cores each, one in each of the MCU and MAIN voltage domains. These clusters are a revised version compared to those present on J721E SoCs. Update the K3 R5F remoteproc bindings with the compatible info relevant to these R5F clusters/subsystems on K3 J7200 SoCs. Signed-off-by: NSuman Anna <s-anna@ti.com>
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由 Suman Anna 提交于
The commit 316c9271 ("include: configs: j721e_evm: Add env variables for mcu_r5fss0_core0 & main_r5fss0_core0") added four different new env variables 'addr_mainr5f0_0load', 'name_mainr5f0_0fw', 'addr_mcur5f0_0load' and 'name_mcur5f0_0fw' to the generic environment, but these are only needed and used in R5 SPL for early-booting the MCU R5FSS0 and Main R5FSS0 Core0 on J721E SoCs. These are not really needed for A72 U-Boot, so limit the scope of these variables only to R5 SPL. While at this, also fix the loadaddr variable values to include the hex prefix like with other such env variables. Cc: Keerthy <j-keerthy@ti.com> Signed-off-by: NSuman Anna <s-anna@ti.com>
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由 Suman Anna 提交于
The default rproc list currently used by A72 U-Boot to boot various remote processors include the Main R5FSS0 (Split-mode) Core1, Main R5FSS1 (LockStep mode) Core0 and the three DSPs. The Main R5FSS1 cluster is configured for Split mode by default in the dts now, so add the Main R5FSS1 Core1 (rproc #5) to the default rproc boot list. This core is now booted after the Main R5FSS1 Core0 and before the DSPs. The order of the rprocs to boot can always be changed at runtime if desired by overwriting the 'rproc_fw_binaries' environment variable at U-boot prompt. Note that the R5FSS Core1 cannot be booted before its associated Core0. Signed-off-by: NSuman Anna <s-anna@ti.com>
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由 Suman Anna 提交于
Switch the MAIN R5FSS1 cluster to be configured for Split-mode as the default so that two different applications can be run on each of the R5F cores in performance mode. LockStep-mode would be available only on SoCs efused with the appropriate bit, and Split-mode is the mode that is available on all J721E SoCs. Signed-off-by: NSuman Anna <s-anna@ti.com>
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由 Vignesh Raghavendra 提交于
Add memory mapped address location of U-Boot images in HyperFlash boot mode. Signed-off-by: NVignesh Raghavendra <vigneshr@ti.com>
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由 Vignesh Raghavendra 提交于
Enable configs required to support HyperFlash boot and detection of onboard mux switch for HyperFlash selection Signed-off-by: NVignesh Raghavendra <vigneshr@ti.com>
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由 Vignesh Raghavendra 提交于
Enable HyperBus and HyperFlash to support HyperFlash boot. Signed-off-by: NVignesh Raghavendra <vigneshr@ti.com>
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由 Vignesh Raghavendra 提交于
On J7200 SoC OSPI and HypeFlash are muxed at HW level and only one of them can be used at any time. J7200 EVM has both HyperFlash and OSPI flash on board. There is a user switch (SW3.1) that can be toggled to select OSPI flash vs HyperFlash. Read the state of this switch via wkup_gpio0_6 line and fixup the DT nodes to select OSPI vs HyperFlash Signed-off-by: NVignesh Raghavendra <vigneshr@ti.com>
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由 Vignesh Raghavendra 提交于
HBMC controller on TI K3 SoC provides MMIO access to HyperFlash similar to legacy Parallel CFI NOR flashes. Therefore alias HyperFlash bootmode to NOR boot to enable SPL to load next stage using NOR boot flow. Signed-off-by: NVignesh Raghavendra <vigneshr@ti.com>
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- 11 9月, 2020 1 次提交
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由 Tom Rini 提交于
- Assorted improvements for MediaTek, Broadcom NS3 and ASPEED SoCs.
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- 10 9月, 2020 8 次提交
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Include ast2500-evb.dtb for CONFIG_ASPEED_AST2500 instead of for all aspeed targets. ast2400 is based on ARM926EJ-S processor (ARMv5-architecture). ast2500 is based on ARM1176JZS processor (ARMv6-architecture). ast2600 is based on Cortex A7 processor (ARMv7-A architecture). Each of the above SOC is using a different ARM CPU(s) with different ARM architecture revision. It is not possible to support all 3 of these families in a single binary. So there is no need to build ast2500-evb.dtb for other SOC families. Signed-off-by: NThirupathaiah Annapureddy <thiruan@linux.microsoft.com>
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由 Chuanjia Liu 提交于
On the mt7623 platform, if one port enable fail and other port enable succeed. It will hang on when using pci enum because the resource was not released correctly. Signed-off-by: NChuanjia Liu <Chuanjia.Liu@mediatek.com> Tested-by: NFrank Wunderlich <frank-w@public-files.de>
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由 Robert Marko 提交于
Import Qualcomm IPQ4019 GCC bindings from Linux. This will enable using bindings instead of raw clock numbers both in the driver and DTS like Linux does. Signed-off-by: NRobert Marko <robert.marko@sartura.hr> Cc: Luka Perkov <luka.perkov@sartura.hr>
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由 Ryan Chen 提交于
Modify SPDX-License for furture patch warning Signed-off-by: NRyan Chen <ryan_chen@aspeedtech.com> Reviewed-by: NChia-Wei, Wang <chiawei_wang@aspeedtech.com>
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由 Ryan Chen 提交于
v2: modify title description aspeed:clock -> clock:aspeed Use kernel include/dt-bindings/clock/aspeed-clock.h define for clock driver. Signed-off-by: NRyan Chen <ryan_chen@aspeedtech.com> Reviewed-by: NChia-Wei, Wang <chiawei_wang@aspeedtech.com>
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由 Ryan Chen 提交于
Rename the ast2500-scu.h to aspeed-clock.h. Signed-off-by: NRyan Chen <ryan_chen@aspeedtech.com> Reviewed-by: NChia-Wei, Wang <chiawei_wang@aspeedtech.com> Reviewed-by: NCédric Le Goater <clg@kaod.org>
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由 Rayagonda Kokatanur 提交于
Chimp is a core in Broadcom netxtream controller (bnxt). Add support to check bnxt's chimp component status. Signed-off-by: NRayagonda Kokatanur <rayagonda.kokatanur@broadcom.com> Reviewed-by: NSimon Glass <sjg@chromium.org>
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由 Rayagonda Kokatanur 提交于
Update MAINTAINERS file for new files. Signed-off-by: NRayagonda Kokatanur <rayagonda.kokatanur@broadcom.com> Reviewed-by: NSimon Glass <sjg@chromium.org>
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