Conflicts:

	MAINTAINERS
Signed-off-by: NWolfgang Denk <wd@denx.de>

Run fixups based on the JEDEC manufacturer ID independent of the
command set ID.

This changes current behaviour: Previously, geometry reversal for AMD
chips were done based on the command set ID, while they are now done
based on the JEDEC manufacturer and device ID.

Also add fixup for top-boot Atmel chips. A fixup is needed for
AT49BV6416(T) too, but since u-boot currently only reads the low byte
of the device ID, there's no way to tell it apart from AT49BV642D,
which should not have this fixup. Since AT49BV642D support is
necessary to get ATNGW100 board support into mainline, I've commented
out the fixup for now.
Signed-off-by: NHaavard Skinnemoen <hskinnemoen@atmel.com>

Move things like reading JEDEC IDs and fixing up geometry reversal
into separate functions. The geometry reversal fixup is now performed
by altering the qry structure directly, which makes the sector init
code slightly cleaner.
Signed-off-by: NHaavard Skinnemoen <hskinnemoen@atmel.com>

Read out the whole CFI Standard Query structure after successful cfi
identification. This allows subsequent code to access this information
directly without having to go through flash_read_uchar() and friends.
Signed-off-by: NHaavard Skinnemoen <hskinnemoen@atmel.com>

disable_interrupts() should return nonzero if interrupts were
_enabled_ before, not disabled.
Signed-off-by: NHaavard Skinnemoen <hskinnemoen@atmel.com>

The timer code depends on the timer interrupt to keep track of the
upper 32 bits of the cycle counter. This obviously doesn't work when
interrupts are disabled the whole time.
Signed-off-by: NHaavard Skinnemoen <hskinnemoen@atmel.com>

As reported by Gerhard Berghofer:

in "gpio_enable_usart3" the correct pins for USART 3 are PB17 and PB18
instead of PB18 and PB19.

which is obviously correct. There's currently no code that uses
USART3, but custom boards may run into problems.
Signed-off-by: NHaavard Skinnemoen <hskinnemoen@atmel.com>

As noted by Kim Phillips, these lists tend to become out of date.
Signed-off-by: NHaavard Skinnemoen <hskinnemoen@atmel.com>

Add all the ATSTK1000 daughterboards to MAINTAINERS along with their
"mother". Also update the entry for ATSTK1000 to be not only about the
AP7000 CPU; it's intended to handle all CPUs in the AT32AP family.
Signed-off-by: NHaavard Skinnemoen <hskinnemoen@atmel.com>

ATSTK1004 is a daughterboard for ATSTK1000 with the AT32AP7002 CPU,
which is a derivative of AT32AP7000.
Signed-off-by: NHaavard Skinnemoen <hskinnemoen@atmel.com>

ATSTK1003 is a daughterboard for ATSTK1000 with the AT32AP7001 CPU,
which is a derivative of AT32AP7000.
Signed-off-by: NHaavard Skinnemoen <hskinnemoen@atmel.com>

Add a chip-features file providing definitions of the form

AT32AP700x_CHIP_HAS_<peripheral>

to indicate the availability of the given peripheral on the currently
selected chip.
Signed-off-by: NHaavard Skinnemoen <hskinnemoen@atmel.com>

The SoC-specific code for all the AT32AP700x CPUs is practically
identical; the only difference is that some chips have less features
than others. By doing this rename, we can add support for the AP7000
derivatives simply by making some features conditional.
Signed-off-by: NHaavard Skinnemoen <hskinnemoen@atmel.com>

Show controller status as well as card status when an error occurs
during block read.
Signed-off-by: NHaavard Skinnemoen <hskinnemoen@atmel.com>

Use map_physmem() and unmap_physmem() to convert from physical to
virtual addresses. This gives the arch a chance to provide an uncached
mapping for flash accesses.
Signed-off-by: NHaavard Skinnemoen <hskinnemoen@atmel.com>

map_physmem() returns a virtual address which can be used to access a
given physical address without involving the cache. unmap_physmem()
should be called when the virtual address returned by map_physmem() is
no longer needed.

This patch adds a stub implementation which simply returns the
physical address cast to a uchar * for all architectures except AVR32,
which converts the physical address to an uncached virtual mapping.
unmap_physmem() is a no-op on all architectures, but if any
architecture needs to do such mappings through the TLB, this is the
hook where those TLB entries can be invalidated.
Signed-off-by: NHaavard Skinnemoen <hskinnemoen@atmel.com>

Introduce flash_read{8,16,32,64) and flash_write{8,16,32,64} and use
them to access the flash memory. This makes it clearer when the flash
is actually being accessed; merely dereferencing a volatile pointer
looks just like any other kind of access.
Signed-off-by: NHaavard Skinnemoen <hskinnemoen@atmel.com>

This adds implementations of __raw_read[bwl] and __raw_write[bwl] to
m68k, ppc, nios and nios2. The m68k and ppc implementations were taken
from Linux.
Signed-off-by: NHaavard Skinnemoen <hskinnemoen@atmel.com>

Reorder the functions in cfi_flash.c so that each function only uses
functions that have been defined before it. This allows the static
prototype declarations near the top to be eliminated and might allow
gcc to do a better job inlining functions.
Signed-off-by: NHaavard Skinnemoen <hskinnemoen@atmel.com>

Make functions not declared in any header file static.
Signed-off-by: NHaavard Skinnemoen <hskinnemoen@atmel.com>

This patch tries to keep all lines in the cfi_flash driver below 80
columns. There are a few lines left which don't fit this requirement
because I couldn't find any trivial way to break them (i.e. it would
take some restructuring, which I intend to do in a later patch.)
Signed-off-by: NHaavard Skinnemoen <hskinnemoen@atmel.com>

Fixes non-working CFI Flash on the Inka4x0 board.
Signed-off-by: NBartlomiej Sieka <tur@semihalf.com>

On the MPC85xx boards that have PCIe enable the PCIe errata fix.
(MPC8544DS, MPC8548CDS, MPC8568MDS).
Signed-off-by: NKumar Gala <galak@kernel.crashing.org>

* Enabled CONFIG_CMD_ELF
Signed-off-by: NKumar Gala <galak@kernel.crashing.org>

The MPC8572 introduces the concept of an asynchronous DDR clock with
regards to the platform clock.

Introduce get_ddr_freq() to report the DDR freq regardless of sync/async
mode.
Signed-off-by: NKumar Gala <galak@kernel.crashing.org>

* Removed some misc environment setup
* Enabled CONFIG_CMDLINE_EDITING
Signed-off-by: NKumar Gala <galak@kernel.crashing.org>

Minor path corrections needed to ensure buildability.
Signed-off-by: NKumar Gala <galak@kernel.crashing.org>

Minor path corrections needed to ensure buildability.
Signed-off-by: NKumar Gala <galak@kernel.crashing.org>

Minor path corrections needed to ensure buildability.
Signed-off-by: NKumar Gala <galak@kernel.crashing.org>

Minor path corrections needed to ensure buildability.
Signed-off-by: NKumar Gala <galak@kernel.crashing.org>

We already had defines for LAWAR_TRGT_IF_* that we should use
rather than creating new ones.  Also, added some missing defines for
PCIE targets.
Signed-off-by: NKumar Gala <galak@kernel.crashing.org>

In the future the offsets to various blocks may not be in same location.
Move to using CFG_MPC85xx_*_ADDR as the base of the registers
instead of getting it via &immap.
Signed-off-by: NKumar Gala <galak@kernel.crashing.org>

Signed-off-by: NKumar Gala <galak@kernel.crashing.org>

Updated the MPC8568 MDS config to use libfdt and assume use of aliases for
ethernet, pci, and serial for the various fixups that are done.
Signed-off-by: NKumar Gala <galak@kernel.crashing.org>

Signed-off-by: NHaiying Wang <Haiying.Wang@freescale.com>
Signed-off-by: NKumar Gala <galak@kernel.crashing.org>