1. 19 10月, 2008 1 次提交
  2. 11 9月, 2008 2 次提交
  3. 13 8月, 2008 1 次提交
  4. 10 7月, 2008 2 次提交
  5. 21 5月, 2008 1 次提交
    • W
      Big white-space cleanup. · 53677ef1
      Wolfgang Denk 提交于
      This commit gets rid of a huge amount of silly white-space issues.
      Especially, all sequences of SPACEs followed by TAB characters get
      removed (unless they appear in print statements).
      
      Also remove all embedded "vim:" and "vi:" statements which hide
      indentation problems.
      Signed-off-by: NWolfgang Denk <wd@denx.de>
      53677ef1
  6. 27 3月, 2008 2 次提交
    • L
      ppc4xx: Updates to Korat-specific code · 6433fa20
      Larry Johnson 提交于
      This patch contains updates for changes for the Korat PPC440EPx board.
      These changes include:
      
      (1) Support for "permanent" and "upgradable" copies of U-Boot, as
      described in the new "doc/README.korat" file;
      
      (2) a new memory map for the registers in the board's CPLD;
      
      (3) a revised format for manufacturer's data in serial EEPROM; and
      
      (4) changes to track updates to U-Boot for the Sequoia board.
      Signed-off-by: NLarry Johnson <lrj@acm.org>
      6433fa20
    • S
      ppc: Add CFG_MEM_TOP_HIDE option to hide memory area that doesn't get "touched" · 14f73ca6
      Stefan Roese 提交于
      If CFG_MEM_TOP_HIDE is defined in the board config header, this specified
      memory area will get subtracted from the top (end) of ram and won't get
      "touched" at all by U-Boot. By fixing up gd->ram_size the Linux kernel
      should gets passed the now "corrected" memory size and won't touch it
      either. This should work for arch/ppc and arch/powerpc. Only Linux board
      ports in arch/powerpc with bootwrapper support, which recalculate the
      memory size from the SDRAM controller setup, will have to get fixed
      in Linux additionally.
      
      This patch enables this config option on some PPC440EPx boards as a workaround
      for the CHIP 11 errata. Here the description from the AMCC documentation:
      
      CHIP_11: End of memory range area restricted access.
      Category: 3
      
      Overview:
      The 440EPx DDR controller does not acknowledge any
      transaction which is determined to be crossing over the
      end-of-memory-range boundary, even if the starting address is
      within valid memory space. Any such transaction from any PLB4
      master will result in a PLB time-out on PLB4 bus.
      
      Impact:
      In case of such misaligned bursts, PLB4 masters will not
      retrieve any data at all, just the available data up to the
      end of memory, especially the 440 CPU. For example, if a CPU
      instruction required an operand located in memory within the
      last 7 words of memory, the DCU master would burst read 8
      words to update the data cache and cross over the
      end-of-memory-range boundary. Such a DCU read would not be
      answered by the DDR controller, resulting in a PLB4 time-out
      and ultimately in a Machine Check interrupt. The data would
      be inaccessible to the CPU.
      
      Workaround:
      Forbid any application to access the last 256 bytes of DDR
      memory. For example, make your operating system believe that
      the last 256 bytes of DDR memory are absent. AMCC has a patch
      that does this, available for Linux.
      
      This patch sets CFG_MEM_TOP_HIDE for the following 440EPx boards:
      lwmon5, korat, sequoia
      
      The other remaining 440EPx board were intentionally not included
      since it is not clear to me, if they use the end of ram for some
      other purpose. This is unclear, since these boards have CONFIG_PRAM
      defined and even comments like this:
      
      PMC440.h:
      /* esd expects pram at end of physical memory.
       * So no logbuffer at the moment.
       */
      
      It is strongly recommended to not use the last 256 bytes on those
      boards too. Patches from the board maintainers are welcome.
      Signed-off-by: NStefan Roese <sr@denx.de>
      14f73ca6
  7. 07 3月, 2008 1 次提交
  8. 03 3月, 2008 1 次提交
  9. 16 2月, 2008 1 次提交
  10. 12 1月, 2008 1 次提交
  11. 04 1月, 2008 1 次提交
  12. 28 12月, 2007 1 次提交