1. 25 4月, 2017 1 次提交
  2. 14 4月, 2017 2 次提交
  3. 18 2月, 2017 1 次提交
    • D
      SPL: add support to boot from a partition type · f0fb4fa7
      Dalon Westergreen 提交于
      the socfpga bootrom supports mmc booting from either a raw image
      starting at 0x0, or from a partition of type 0xa2.  This patch
      adds support for locating the boot image in the first type 0xa2
      partition found.
      
      Assigned a partition number of -1 will cause a search for a
      partition of type CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_PARTITION_TYPE
      and use it to find the u-boot image
      Signed-off-by: NDalon Westergreen <dwesterg@gmail.com>
      f0fb4fa7
  4. 24 1月, 2017 1 次提交
  5. 06 12月, 2016 1 次提交
  6. 17 9月, 2016 9 次提交
  7. 08 6月, 2016 2 次提交
  8. 02 6月, 2016 1 次提交
    • M
      arm: socfpga: Add samtec VIN|ING board · 569a191a
      Marek Vasut 提交于
      Add support for board based on the popular Altera Cyclone V SoC.
      This board has the following properties:
       - 1 GiB of DRAM
       - 1 Gigabit ethernet
       - 1 USB gadget port
       - 1 USB host port with an on-board hub
       - 2 QSPI NORs connected to the Cadence QSPI core
       - Multiple I2C EEPROMs and one I2C temperature sensor
      Signed-off-by: NMarek Vasut <marex@denx.de>
      Cc: Dinh Nguyen <dinguyen@opensource.altera.com>
      Cc: Chin Liang See <clsee@altera.com>
      ---
      V2: Update the defconfig as per Tom's request
      569a191a
  9. 20 12月, 2015 1 次提交
  10. 07 12月, 2015 1 次提交
  11. 30 11月, 2015 1 次提交
    • M
      arm: socfpga: Repair SoCrates board · 856b30da
      Marek Vasut 提交于
      This board was constantly parasiting on the CV SoCDK, so split it
      into it's own separate directory. Moreover, the board config was
      missing important bits, like simple-bus support in SPL, the DRAM
      configuration was incorrect and the DTS was also missing the pre
      reloc bits.
      Signed-off-by: NMarek Vasut <marex@denx.de>
      Cc: Stefan Roese <sr@denx.de>
      Cc: Dinh Nguyen <dinguyen@opensource.altera.com>
      Cc: Dinh Nguyen <dinh.linux@gmail.com>
      Cc: Jan Viktorin <viktorin@rehivetech.com>
      856b30da
  12. 23 9月, 2015 1 次提交
  13. 04 9月, 2015 3 次提交
  14. 23 8月, 2015 2 次提交
    • M
      arm: socfpga: Split Altera socfpga into AV and CV SoCDK · f0892401
      Marek Vasut 提交于
      The board/altera/socfpga directory is not a generic SoCFPGA machine
      anymore, but instead it represents the Altera SoCDK board. To make
      matters more complicated, it represents both CycloneV and ArriaV
      variant.
      
      On the other hand, nowadays, the content of this board directory is
      mostly comprised of QTS-generated header files, while all the generic
      code is in arch/arm/mach-socfpga already.
      
      Thus, this patch splits the board/altera/socfpga into a separate
      board directory for ArriaV SoCDK and CycloneV SoCDK, so that each
      can be populated with the correct QTS-generated header files for
      that particular board.
      Signed-off-by: NMarek Vasut <marex@denx.de>
      f0892401
    • M
      arm: socfpga: Unbind CPU type from board type · cd9b7317
      Marek Vasut 提交于
      The CONFIG_TARGET_SOCFPGA_CYCLONE5 and CONFIG_TARGET_SOCFPGA_ARRIA5
      selected both a board and a CPU. This is not correct as these macros
      are supposed to select only board.
      
      All would be good, if QTS-generated header files didn't check for
      these macros exactly to determine if the platform is Cyclone V or
      Arria V. Thus, for the sake of compatibility with not well fleshed
      out header file generator, this patch makes these two macros into
      a stub config option and introduces new CONFIG_TARGET_SOCFPGA_CYCLONE5_SOCDK
      and CONFIG_TARGET_SOCFPGA_ARRIA5_SOCDK targets, which select the
      previous stub config option.
      
      The result is that compatibility with QTS is preserved and the new
      CONFIG_TARGET_* select actual target boards.
      Signed-off-by: NMarek Vasut <marex@denx.de>
      cd9b7317
  15. 13 5月, 2015 1 次提交
  16. 07 5月, 2015 1 次提交