- 22 10月, 2020 4 次提交
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由 Patrick Delaunay 提交于
Cosmetic update of gpio.h: - remove enumerate: stm32_gpio_port, stm32_gpio_pin because STM32_GPIO_XXX values are unused - move STM32_GPIOS_PER_BANK in stm32_gpio.c as its value is IP dependent and not arch dependent No functional change as number of banks and number of gpio by banks is managed by device tree since since DM migration and commit 8f651ca6 ("pinctrl: stm32: Add get_pins_count() ops"). Signed-off-by: NPatrick Delaunay <patrick.delaunay@st.com> Reviewed-by: NPatrice Chotard <patrice.chotard@st.com>
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由 Marek Vasut 提交于
In case the KS8851 has external EEPROM attached to it, do not set eth1addr at all. The network stack will read the MAC out of the KS8851 and set eth1addr accordingly. Signed-off-by: NMarek Vasut <marex@denx.de> Cc: Patrice Chotard <patrice.chotard@st.com> Cc: Patrick Delaunay <patrick.delaunay@st.com> Reviewed-by: NPatrice Chotard <patrice.chotard@st.com> Reviewed-by: NPatrick Delaunay <patrick.delaunay@st.com>
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由 Patrick Delaunay 提交于
In pre-reloc stage, U-Boot marks cacheable the DDR limited by the new config CONFIG_DDR_CACHEABLE_SIZE. This patch allows to avoid any speculative access to DDR protected by firewall and used by OP-TEE; the "no-map" reserved memory node in DT are assumed after this limit: STM32_DDR_BASE + DDR_CACHEABLE_SIZE. Without security, in basic boot, the value is equal to STM32_DDR_SIZE. Signed-off-by: NPatrick Delaunay <patrick.delaunay@st.com> Reviewed-by: NPatrice Chotard <patrice.chotard@st.com>
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由 Alexandru Gagniuc 提交于
mmc_of_parse() can populate the 'f_max' and 'host_caps' fields of struct mmc_config from devicetree. The same logic is duplicated in stm32_sdmmc2_probe(). Use mmc_of_parse(), which is more generic. Signed-off-by: NAlexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-by: NPatrice Chotard <patrice.chotard@st.com> Reviewed-by: NJaehoon Chung <jh80.chung@samsung.com>
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- 21 10月, 2020 1 次提交
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由 Alexandru Gagniuc 提交于
"cap-mmc-highspeed" enables support for 26 MHz MMC, but there is no additional flag to enable 52 MHz MMC. In Linux. "cap-mmc-highspeed" is used for MMC HS at both 26MHz and 52MHz. Use the same approach and enable MMC_CAP(MMC_HS_52) host capability when "cap-mmc-highspeed" is found in the devicetree. In the event an MMC card doesn't support 52 MHz, it will be clocked at a speed based on its EXT CSD, even on 52 MHz host controllers Signed-off-by: NAlexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-by: NPatrick Delaunay <patrick.delaunay@st.com> Tested-by: NPatrick Delaunay <patrick.delaunay@st.com> Reviewed-by: NPatrice Chotard <patrice.chotard@st.com>
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- 19 10月, 2020 13 次提交
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https://gitlab.denx.de/u-boot/custodians/u-boot-atmel由 Tom Rini 提交于
Second set of u-boot-atmel features for 2021.01 cycle: This feature set brings the rework of the clock tree for sam9x60 SoC. This makes the clock tree fully compatible with Common Clock Framework and allows full clock configuration in U-Boot. This means that the sam9x60 boards can boot now using U-Boot. This also includes the definitions for sam9x60 SiPs and a divisor fix for the clock on sama7g5 SoC.
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由 Eugen Hristev 提交于
This SoC has the 5th divisor for the mck0 master clock. Adapt the characteristics accordingly. Reported-by: NMihai Sain <mihai.sain@microchip.com> Signed-off-by: NEugen Hristev <eugen.hristev@microchip.com> Reviewed-by: NClaudiu Beznea <claudiu.beznea@microchip.com>
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由 Eugen Hristev 提交于
clk-master can have 5 divisors with a field width of 3 bits on some products. Change the mask and number of divisors accordingly. Reported-by: NMihai Sain <mihai.sain@microchip.com> Signed-off-by: NEugen Hristev <eugen.hristev@microchip.com> Reviewed-by: NClaudiu Beznea <claudiu.beznea@microchip.com>
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由 Nicolas Ferre 提交于
SAM9X60 SiP (System in Package) are added for SoC identification. Signed-off-by: NNicolas Ferre <nicolas.ferre@microchip.com>
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由 Claudiu Beznea 提交于
Use alphabetical order for entries in sam9x60ek-u-boot.dtsi Signed-off-by: NClaudiu Beznea <claudiu.beznea@microchip.com>
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由 Claudiu Beznea 提交于
Update defconfigs for using common clock framework compatible clocks. Signed-off-by: NClaudiu Beznea <claudiu.beznea@microchip.com>
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由 Claudiu Beznea 提交于
Use CCF compatible for PMC. With this, the board/SoC will be able to boot. Signed-off-by: NClaudiu Beznea <claudiu.beznea@microchip.com>
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由 Claudiu Beznea 提交于
Use slow clock CCF compatible DT bindings. This will not break the above functionality as the SoC is not booting with current PMC bindings. Signed-off-by: NClaudiu Beznea <claudiu.beznea@microchip.com>
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由 Claudiu Beznea 提交于
Use u-boot,dm-pre-reloc for slow xtal and main xtal. Signed-off-by: NClaudiu Beznea <claudiu.beznea@microchip.com>
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由 Claudiu Beznea 提交于
Slow Xtal and Main Xtal are board specific. Add their proper frequency to board file. Signed-off-by: NClaudiu Beznea <claudiu.beznea@microchip.com>
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由 Claudiu Beznea 提交于
Add SAM9X60 clock support compatible with CCF. Signed-off-by: NClaudiu Beznea <claudiu.beznea@microchip.com>
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由 Claudiu Beznea 提交于
Heap base address is computed based on SYS_INIT_SP_ADDR by subtracting the SYS_MALLOC_F_LEN value in board_init_f_init_reserve(). Signed-off-by: NClaudiu Beznea <claudiu.beznea@microchip.com>
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https://gitlab.denx.de/u-boot/custodians/u-boot-video由 Tom Rini 提交于
- add dw-mipi-dsi phy timings and Tx escape clock configuration - fix pwm backlight duty cycle calculation - migrate CONFIG_VIDEO_BMP_* and CONFIG_BMP_* to Kconfig
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- 18 10月, 2020 7 次提交
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由 Patrick Delaunay 提交于
Done with: ./tools/moveconfig.py BMP_16BPP BMP_24BPP BMP_32BPP Signed-off-by: NPatrick Delaunay <patrick.delaunay@st.com> Reviewed-by: NSimon Glass <sjg@chromium.org>
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由 Patrick Delaunay 提交于
Done with: ./tools/moveconfig.py VIDEO_BMP_RLE8 Signed-off-by: NPatrick Delaunay <patrick.delaunay@st.com> Reviewed-by: NSimon Glass <sjg@chromium.org>
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由 Patrick Delaunay 提交于
Done with: ./tools/moveconfig.py VIDEO_BMP_GZIP The 3 suspicious migration because CMD_BMP and SPLASH_SCREEN are not activated in these defconfigs: - trats_defconfig - s5pc210_universal_defconfig - trats2_defconfig Signed-off-by: NPatrick Delaunay <patrick.delaunay@st.com> Reviewed-by: NSimon Glass <sjg@chromium.org>
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由 Dario Binacchi 提交于
For levels equal to the maximum value, the duty cycle must be equal to the period. Signed-off-by: NDario Binacchi <dariobin@libero.it> Reviewed-by: NSimon Glass <sjg@chromium.org>
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由 Dario Binacchi 提交于
The description of the 'max_level' field was incorrectly assigned to the 'min_level' field. Signed-off-by: NDario Binacchi <dariobin@libero.it>
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由 Neil Armstrong 提交于
The Amlogic D-PHY in the Amlogic AXG SoC Family does support a frequency higher than 10MHz for the TX Escape Clock, thus make the target rate configurable. This is based on the Linux commit [1] and adapted to the U-Boot driver. [1] a328ca7e4af3 ("drm/bridge: dw-mipi-dsi: permit configuring the escape clock rate") Signed-off-by: NNeil Armstrong <narmstrong@baylibre.com>
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由 Neil Armstrong 提交于
The timing values for dw-dsi are often dependent on the used display and according to Philippe Cornu will most likely also depend on the used phy technology in the soc-specific implementation. To solve this and allow specific implementations to define them as needed add a new get_timing callback to phy_ops and call this from the dphy_timing function to retrieve the necessary values for the specific mode. This is based on the Linux commit [1] and adapted to the U-Boot driver. [1] 25ed8aeb9c39 ("drm/bridge/synopsys: dsi: driver-specific configuration of phy timings") Signed-off-by: NNeil Armstrong <narmstrong@baylibre.com>
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- 17 10月, 2020 1 次提交
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由 Sean Anderson 提交于
syslog_test.h is in test/log/, not include/ Fixes: 52d3df7f ("log: Allow LOG_DEBUG to always enable log output") Signed-off-by: NSean Anderson <seanga2@gmail.com> Reviewed-by: NSimon Glass <sjg@chromium.org>
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- 16 10月, 2020 14 次提交
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https://gitlab.denx.de/u-boot/custodians/u-boot-marvell由 Tom Rini 提交于
- Fix Octeon SPI driver for Octeon TX2 - Fix and enhance Octeon watchdog driver - Misc minor enhancements to Octeon TX/TX2
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由 Tom Rini 提交于
- Bring in the next round of dev_xxx cleanup patches.
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由 Sean Anderson 提交于
Now that linux/compat.h does not define these macros, we do not need to undefine them. Signed-off-by: NSean Anderson <seanga2@gmail.com> Reviewed-by: NSimon Glass <sjg@chromium.org>
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由 Sean Anderson 提交于
All users of these functions now include dm/device_compat.h directly. Signed-off-by: NSean Anderson <seanga2@gmail.com> Reviewed-by: NSimon Glass <sjg@chromium.org>
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由 Tom Rini 提交于
Necessary for dev_xxx. Signed-off-by: NTom Rini <trini@konsulko.com>
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由 Tom Rini 提交于
Necessary for dev_xxx. Signed-off-by: NTom Rini <trini@konsulko.com>
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由 Tom Rini 提交于
Necessary for dev_xxx. Signed-off-by: NTom Rini <trini@konsulko.com>
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由 Sean Anderson 提交于
This driver doesn't use DM (in the correct places), so we use a device and not a udevice. We also need to include device_compat.h Signed-off-by: NSean Anderson <seanga2@gmail.com>
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由 Sean Anderson 提交于
This was included, but was ifdef'd out. We also need dm.h for struct udevice. Signed-off-by: NSean Anderson <seanga2@gmail.com>
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由 Sean Anderson 提交于
This header is necessary for the dev_xxx macros. Signed-off-by: NSean Anderson <seanga2@gmail.com>
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由 Sean Anderson 提交于
Necessary for dev_xxx. Signed-off-by: NSean Anderson <seanga2@gmail.com> Reviewed-by: NSimon Glass <sjg@chromium.org>
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由 Sean Anderson 提交于
Necessary for dev_xxx. Signed-off-by: NSean Anderson <seanga2@gmail.com> Reviewed-by: NSimon Glass <sjg@chromium.org>
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由 Sean Anderson 提交于
Necessary for dev_xxx. Signed-off-by: NSean Anderson <seanga2@gmail.com>
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由 Sean Anderson 提交于
Necessary for dev_xxx. Signed-off-by: NSean Anderson <seanga2@gmail.com>
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