- 04 7月, 2011 25 次提交
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由 Andreas Bießmann 提交于
This patch enables the new clock features from arm920t/at91/clock.c. This is an required step to get at91rm9200_usart replaced by atmel_usart driver. Signed-off-by: NAndreas Bießmann <andreas.devel@googlemail.com> Cc: Jens Scharsig <js_at_ng@scharsoft.de> Cc: Eric Bénard <eric@eukrea.com>
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由 Andreas Bießmann 提交于
This patch adds an copy of arm926ejs/at91/clock.c to arm920t/at91. The arm926ejs specialities are removed from arm920t version and vice versa. Signed-off-by: NAndreas Bießmann <andreas.devel@googlemail.com>
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由 Andreas Bießmann 提交于
This patch sets the ATMEL_PMX_AA_TXD2 to the correct value. Signed-off-by: NAndreas Bießmann <andreas.devel@googlemail.com> CC: Jens Scharsig <js_at_ng@scharsoft.de> CC: eric@eukrea.com Acked-by: NEric Bénard <eric@eukrea.com>
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由 Fabio Estevam 提交于
commit 0015de1a (MX5: Make the weim structure complete) fixed the name for the WEIM registers in order to match with the MX51/MX53 manuals. Fix the WEIM register for vision2 board so that it can build again. Signed-off-by: NFabio Estevam <fabio.estevam@freescale.com>
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由 Fabio Estevam 提交于
Signed-off-by: NFabio Estevam <fabio.estevam@freescale.com>
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由 Fabio Estevam 提交于
Signed-off-by: NFabio Estevam <fabio.estevam@freescale.com>
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由 Fabio Estevam 提交于
Signed-off-by: NFabio Estevam <fabio.estevam@freescale.com>
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由 Fabio Estevam 提交于
Signed-off-by: NFabio Estevam <fabio.estevam@freescale.com>
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由 Matthias Weisser 提交于
Enable dcache and arch memset/memcpy for speed reasons Remove of config.mk and some environment overwrites Some generic cleanup Signed-off-by: NMatthias Weisser <weisserm@arcor.de>
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由 Igor Grinberg 提交于
Define CONFIG_SYS_SDRAM_BASE to physical SDRAM address and CONFIG_SYS_INIT_SP_ADDR to physical SRAM address Signed-off-by: NIgor Grinberg <grinberg@compulab.co.il> Cc: Kyungmin Park <kyungmin.park@samsung.com>
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由 John Rigby 提交于
As implemented now the timer used to implement __udelay counts to 0xffffffff and then gets stuck there because the the programmed reload value is 0xffffffff. This value is not only wrong but illegal according to the reference manual. One can reproduce the bug by leaving a board at the u-boot prompt for sometime then issuing a sleep command. The sleep will hang forever. The timer is a count up timer that reloads as it rolls over from 0xffffffff so the correct load value is 0. Change TIMER_LOAD_VAL from 0xffffffff to 0 and introduce a new constant called TIMER_OVERFLOW_VAL set to 0xffffffff. Signed-off-by: NJohn Rigby <john.rigby@linaro.org> Tested-by: NIgor Grinberg <grinberg@compulab.co.il>
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由 Tom Warren 提交于
Signed-off-by: NTom Warren <twarren@nvidia.com>
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由 Tom Warren 提交于
Signed-off-by: NTom Warren <twarren@nvidia.com>
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由 David Müller (ELSOFT AG) 提交于
Signed-off-by: NDavid Müller <d.mueller@elsoft.ch>
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由 David Müller (ELSOFT AG) 提交于
Signed-off-by: NDavid Müller <d.mueller@elsoft.ch>
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由 David Müller (ELSOFT AG) 提交于
Signed-off-by: NDavid Müller <d.mueller@elsoft.ch>
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由 Aneesh V 提交于
adapt s5pc1xx to the new layered cache maintenance framework Signed-off-by: NAneesh V <aneesh@ti.com>
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由 Aneesh V 提交于
adapt omap3 to the new layered cache maintenance framework Signed-off-by: NAneesh V <aneesh@ti.com>
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由 Aneesh V 提交于
adapt omap4 to the new layered cache maintenance framework Signed-off-by: NAneesh V <aneesh@ti.com>
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由 Aneesh V 提交于
PL310 is the L2$ controller from ARM used in many SoCs including the Cortex-A9 based OMAP4430 Add support for some of the key PL310 operations - Invalidate all - Invalidate range - Flush(clean & invalidate) all - Flush range Signed-off-by: NAneesh V <aneesh@ti.com>
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由 Aneesh V 提交于
1. make sure that page table setup is not done multiple times 2. flush_dcache_all() is more appropriate while disabling cache than a range flush on the entire memory(flush_cache()) Provide a default implementation for flush_dcache_all() for backward compatibility and to avoid build issues. Signed-off-by: NAneesh V <aneesh@ti.com>
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由 Aneesh V 提交于
- Enable I-cache on bootup - Enable MMU and D-cache immediately after relocation - Do necessary initialization before enabling d-cache and MMU - Changes to cleanup_before_linux() - Make changes according to the new framework Signed-off-by: NAneesh V <aneesh@ti.com>
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由 Aneesh V 提交于
Replace the cache related CONFIG flags with more meaningful names. Following are the changes: CONFIG_L2_OFF -> CONFIG_SYS_L2CACHE_OFF CONFIG_SYS_NO_ICACHE -> CONFIG_SYS_ICACHE_OFF CONFIG_SYS_NO_DCACHE -> CONFIG_SYS_DCACHE_OFF Signed-off-by: NAneesh V <aneesh@ti.com> V2: * Changed CONFIG_L2_OFF -> CONFIG_SYS_NO_L2CACHE V4: * Changed all three flags to the final names suggested as above and accordingly changed the commit message
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由 Aneesh V 提交于
- Add a framework for layered cache maintenance - separate out SOC specific outer cache maintenance from maintenance of caches known to CPU - Add generic ARMv7 cache maintenance operations that affect all caches known to ARMv7 CPUs. For instance in Cortex-A8 these opertions will affect both L1 and L2 caches. In Cortex-A9 these will affect only L1 cache - D-cache operations supported: - Invalidate entire D-cache - Invalidate D-cache range - Flush(clean & invalidate) entire D-cache - Flush D-cache range - I-cache operations supported: - Invalidate entire I-cache - Add maintenance functions for TLB, branch predictor array etc. - Enable -march=armv7-a so that armv7 assembly instructions can be used Signed-off-by: NAneesh V <aneesh@ti.com>
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由 Aneesh V 提交于
make default implementation of cache_flush() weakly linked so that sub-architectures can override it Signed-off-by: NAneesh V <aneesh@ti.com>
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- 02 7月, 2011 7 次提交
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由 Kumar Gala 提交于
On MPC85xx based NAND_SPL builds we generate a u-boot-nand_spl.lds based on output from preprocessor. We where never removed it. Signed-off-by: NKumar Gala <galak@kernel.crashing.org> Signed-off-by: NScott Wood <scottwood@freescale.com>
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由 Alex Waterman 提交于
This patch adds support for 16 bit NAND devices attached to the NDFC on ppc4xx processors. Two config entries were added: CONFIG_SYS_NDFC_16 - Setting this tells the NDFC that a 16 bit device is attached. CONFIG_SYS_NDFC_EBC0_CFG - This is for the External Bus Controller configuration register. Also, a new ndfc_read_byte() function was added which does not first convert the data to little endian. The NAND SPL was also modified to do 16bit bad block testing when a 16 bit chip is being used. Signed-off-by: NAlex Waterman <awaterman@dawning.com> Signed-off-by: NScott Wood <scottwood@freescale.com>
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由 Ben Gardiner 提交于
Add another nand write. variant, trimffs. This command will request of nand_write_skip_bad() that all trailing all-0xff pages will be dropped from eraseblocks when they are written to flash as-per the reccommended behaviour of the UBI FAQ [1]. The function that implements this timming is the drop_ffs() function by Artem Bityutskiy, ported from the mtd-utils tree. [1] http://www.linux-mtd.infradead.org/doc/ubi.html#L_flasher_algoSigned-off-by: NBen Gardiner <bengardiner@nanometrics.ca> CC: Artem Bityutskiy <dedekind1@gmail.com> CC: Detlev Zundel <dzu@denx.de> Acked-by: NScott Wood <scottwood@freescale.com> Signed-off-by: NScott Wood <scottwood@freescale.com>
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由 Ben Gardiner 提交于
Add a flag to nand_read_skip_bad() such that if true, any trailing pages in an eraseblock whose contents are entirely 0xff will be dropped. The implementation is via a new drop_ffs() function which is based on the function of the same name from the ubiformat utility by Artem Bityutskiy. This is as-per the reccomendations of the UBI FAQ [1] [1] http://www.linux-mtd.infradead.org/doc/ubi.html#L_flasher_algoSigned-off-by: NBen Gardiner <bengardiner@nanometrics.ca> CC: Artem Bityutskiy <dedekind1@gmail.com> Acked-by: NDetlev Zundel <dzu@denx.de> CC: Scott Wood <scottwood@freescale.com> Signed-off-by: NScott Wood <scottwood@freescale.com>
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由 Ben Gardiner 提交于
When specified in the flags argument of nand_write, WITH_YAFFS_OOB causes an operation which is mutually exclusive with the 'usual' way of writing. Add a check that client code does not specify WITH_YAFFS_OOB along with any other flags and add a comment indicating that the WITH_YAFFS_OOB flag should not be mixed with other flags. Signed-off-by: NBen Gardiner <bengardiner@nanometrics.ca> CC: Scott Wood <scottwood@freescale.com> Signed-off-by: NScott Wood <scottwood@freescale.com>
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由 Ben Gardiner 提交于
In a future commit the behaviour of nand_write_skip_bad() will be further extended. Convert the only flag currently passed to the nand_write_ skip_bad() function to a bitfield of only one allocated member. This should avoid an explosion of int's at the end of the parameter list or the ambiguous calls like nand_write_skip_bad(info, offset, len, buf, 0, 1, 1); nand_write_skip_bad(info, offset, len, buf, 0, 1, 0); Instead there will be: nand_write_skip_bad(info, offset, len, buf, WITH_YAFFS_OOB | WITH_OTHER); Signed-off-by: NBen Gardiner <bengardiner@nanometrics.ca> Acked-by: NDetlev Zundel <dzu@denx.de> Signed-off-by: NScott Wood <scottwood@freescale.com>
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由 Ben Gardiner 提交于
Replace an incorrect 'read' with 'write' in a comment. Signed-off-by: NBen Gardiner <bengardiner@nanometrics.ca> Acked-by: NDetlev Zundel <dzu@denx.de> Signed-off-by: NScott Wood <scottwood@freescale.com>
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- 01 7月, 2011 1 次提交
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git://git.denx.de/u-boot-nios由 Wolfgang Denk 提交于
* 'next' of git://git.denx.de/u-boot-nios: nios2: move generic config to boards.cfg
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- 30 6月, 2011 1 次提交
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由 Mike Frysinger 提交于
I can't build test this, but just looking at the config files written and it seems OK ... Tested-by: NThomas Chou <thomas@wytron.com.tw> Signed-off-by: NMike Frysinger <vapier@gentoo.org> Signed-off-by: NScott McNutt <smcnutt@psyent.com>
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- 29 6月, 2011 1 次提交
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由 Mike Frysinger 提交于
For newer STM parts where CFI >= 1.1, there is a byte in the extended structure that declares the flash layout type (just like the AMD parts), so key off of that to find out when we need to reverse the geometry. This can be seen with M29W640 parts where U-Boot does: Bank # 1: CFI conformant FLASH (16 x 16) Size: 8 MB in 135 Sectors AMD Standard command set, Manufacturer ID: 0x20, Device ID: 0x22ED Erase timeout: 8192 ms, write timeout: 1 ms Buffer write timeout: 1 ms, buffer size: 16 bytes Sector Start Addresses: 20000000 RO 20002000 RO 20004000 RO 20006000 RO 20008000 RO 2000A000 RO 2000C000 RO 2000E000 RO 20010000 RO 20020000 RO ... But Linux does: physmap platform flash device: 00800000 at 20000000 physmap-flash.0: Found 1 x16 devices at 0x0 in 16-bit bank. Manufacturer ID 0x000020 Chip ID 0x0022ed physmap-flash.0: Swapping erase regions for top-boot CFI table. Signed-off-by: NMike Frysinger <vapier@gentoo.org> Signed-off-by: NStefan Roese <sr@denx.de>
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- 28 6月, 2011 2 次提交
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由 Wolfgang Denk 提交于
Signed-off-by: NWolfgang Denk <wd@denx.de>
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由 Wolfgang Denk 提交于
Signed-off-by: NWolfgang Denk <wd@denx.de>
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- 25 6月, 2011 3 次提交
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由 Mike Frysinger 提交于
Looks like this was missed during the conversion to partial linking. Signed-off-by: NMike Frysinger <vapier@gentoo.org>
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由 Zhao Chenhui 提交于
Convert the PCI base address into a virtual address. Signed-off-by: NZhao Chenhui <b35336@freescale.com> Signed-off-by: NLi Yang <leoli@freescale.com>
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由 Cliff Cai 提交于
When dealing with non-multipoint devices, if the software root hub code accepted the message, then we still need to process it normally. So only return quickly when the root hub skipped the message or is otherwise in an error state. Signed-off-by: NCliff Cai <cliff.cai@analog.com> Signed-off-by: NMike Frysinger <vapier@gentoo.org>
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