- 15 11月, 2016 40 次提交
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由 Bharat Kumar Gogada 提交于
Adding prefetchable memory space to pcie device tree node. Shifting configuration space to 64-bit address space. Removing pcie device tree node from amba as it requires size-cells=<2> in order to access 64-bit address space. Signed-off-by: NBharat Kumar Gogada <bharatku@xilinx.com> Signed-off-by: NMichal Simek <michal.simek@xilinx.com>
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由 Kedareswara rao Appana 提交于
Zynqmp DMA driver expects two clocks (main clock and apb clock) For LPDDMA channels the two clocks are missing in the Dma node resulting probe failure. xilinx-zynqmp-dma ffa80000.dma: main clock not found. xilinx-zynqmp-dma ffa80000.dma: Probing channel failed xilinx-zynqmp-dma: probe of ffa80000.dma failed with error -2 This patch fixes this issue. Signed-off-by: NKedareswara rao Appana <appanad@xilinx.com> Signed-off-by: NMichal Simek <michal.simek@xilinx.com>
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由 Kedareswara rao Appana 提交于
LPDDMA default allows only secured access. inorder to enable these dma channels, one should ensure that it allows non secure access. This patch updates the same. Reported-by: NSai Pavan Boddu <saipava@xilinx.com> Signed-off-by: NKedareswara rao Appana <appanad@xilinx.com> Signed-off-by: NMichal Simek <michal.simek@xilinx.com>
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由 Michal Simek 提交于
Use 64bit size cell for main amba bus instead of 32bit because PCIe node requires it Change 64bit sizes also for all others IPs. Signed-off-by: NMichal Simek <michal.simek@xilinx.com>
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由 Naga Sureshkumar Relli 提交于
This patch adds ocm controller node in zynqmp.dtsi. needed for OCM edac support. Signed-off-by: NNaga Sureshkumar Relli <nagasure@xilinx.com> Signed-off-by: NMichal Simek <michal.simek@xilinx.com>
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由 Anurag Kumar Vulisha 提交于
This patch adds the ZynqMP GT core device-tree properties for zynqmp.dtsi file. Signed-off-by: NAnurag Kumar Vulisha <anuragku@xilinx.com> Tested-by: NHyun Kwon <hyunk@xilinx.com> Signed-off-by: NMichal Simek <michal.simek@xilinx.com>
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由 Michal Simek 提交于
This reverts commit bd750e7a Implemented the new workaround for auto tuning based on zynqmp compatible string, so removed the 'broken-tuning' property. Signed-off-by: NMichal Simek <michal.simek@xilinx.com>
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由 Sai Krishna Potthuri 提交于
This patch changes the compatible string for sdhci node, adds "xlnx,device_id" and "xlnx,mio_bank" property to sdhci node. Signed-off-by: NSai Krishna Potthuri <lakshmis@xilinx.com> Signed-off-by: NMichal Simek <michal.simek@xilinx.com>
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由 Michal Simek 提交于
Add SMMU description for all tested IPs. Signed-off-by: NMichal Simek <michal.simek@xilinx.com>
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由 Nava kishore Manne 提交于
Add support for zynqmp fpga manager. Signed-off-by: NNava kishore Manne <navam@xilinx.com> Signed-off-by: NMichal Simek <michal.simek@xilinx.com>
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由 Naga Sureshkumar Relli 提交于
This patch adds edac node for arm cortexa53 to report errors on L1 and L2 caches. Signed-off-by: NNaga Sureshkumar Relli <nagasure@xilinx.com> Signed-off-by: NMichal Simek <michal.simek@xilinx.com>
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由 Michal Simek 提交于
This reverts commit 786db82b. Since we are using serdes driver , no need of mapping serdes register space into DP driver. Signed-off-by: NAnurag Kumar Vulisha <anuragku@xilinx.com> Tested-by: NHyun Kwon <hyunk@xilinx.com> Signed-off-by: NMichal Simek <michal.simek@xilinx.com>
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由 Hyun Kwon 提交于
Each plane can be associated with multiple DMA channels. So add index for each DMA channel. Signed-off-by: NHyun Kwon <hyun.kwon@xilinx.com> Signed-off-by: NMichal Simek <michal.simek@xilinx.com>
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由 Michal Simek 提交于
Keep dtsi in sync with mainline kernel. Signed-off-by: NMichal Simek <michal.simek@xilinx.com>
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由 Michal Simek 提交于
Remove unused xlnx,id property because it is not the part of DT binding. Signed-off-by: NMichal Simek <michal.simek@xilinx.com>
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由 Bharat Kumar Gogada 提交于
Updating required device tree changes as per mainlined driver from 4.6 kernel. Signed-off-by: NBharat Kumar Gogada <bharatku@xilinx.com> Signed-off-by: NMichal Simek <michal.simek@xilinx.com>
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由 Filip Drazic 提交于
Previously, it was assumed that there is a 1:1 mapping between PM ID defined in the platform firmware and a PM domain. However, there can be a situation where multiple PM IDs belong to a single PM domain (e.g. PM IDs for GPU and two pixel processors correspond to a single PM domain). This patch adds support for assigning more than one PM ID to a single PM domain. Updated documentation accordingly. Assigned pixel processors PM IDs to GPU PM domain. Signed-off-by: NFilip Drazic <filip.drazic@aggios.com> Signed-off-by: NSoren Brinkmann <soren.brinkmann@xilinx.com> Signed-off-by: NMichal Simek <michal.simek@xilinx.com>
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由 Filip Drazic 提交于
Signed-off-by: NFilip Drazic <filip.drazic@aggios.com> Signed-off-by: NSoren Brinkmann <soren.brinkmann@xilinx.com> Signed-off-by: NMichal Simek <michal.simek@xilinx.com>
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由 Filip Drazic 提交于
Signed-off-by: NFilip Drazic <filip.drazic@aggios.com> Acked-by: NSoren Brinkmann <soren.brinkmann@xilinx.com> Signed-off-by: NMichal Simek <michal.simek@xilinx.com>
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由 Filip Drazic 提交于
DDR power states are handled by the PM firmware, so this domain is redundant. Also, since there is no device using this PM domain, it will be powered off during boot, which is wrong. Signed-off-by: NFilip Drazic <filip.drazic@aggios.com> Acked-by: NSoren Brinkmann <soren.brinkmann@xilinx.com> Signed-off-by: NMichal Simek <michal.simek@xilinx.com>
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由 Michal Simek 提交于
i2c device is just level shifter. Remove reference from dts. Signed-off-by: NMichal Simek <michal.simek@xilinx.com>
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由 Michal Simek 提交于
Add dcc to dtsi for supporting system without serial port. DCC is enabled by default on ZynqMP. Adding dcc to zcu100 and zcu102 which were tested. Signed-off-by: NMichal Simek <michal.simek@xilinx.com>
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由 Michal Simek 提交于
There is gpio push button on MIO22. Add it to DTS to have full board description. Signed-off-by: NMichal Simek <michal.simek@xilinx.com>
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由 Michal Simek 提交于
Show user that Linux is alive on the board. Signed-off-by: NMichal Simek <michal.simek@xilinx.com>
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由 Naga Sureshkumar Relli 提交于
This patch enables can1 for ep108. Signed-off-by: NNaga Sureshkumar Relli <nagasure@xilinx.com> Reviewed-by: NKedareswara rao Appana <appanad@xilinx.com> Signed-off-by: NMichal Simek <michal.simek@xilinx.com>
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由 VNSL Durga 提交于
Added clks for ep108 platform. Signed-off-by: NVNSL Durga <vnsldurg@xilinx.com> Signed-off-by: NMichal Simek <michal.simek@xilinx.com>
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由 Kedareswara rao Appana 提交于
Zynqmp DMA driver expects two clocks (main clock and apb clock) LPDDMA clock cofiguration is missing for the same in the zynqmp-clk.dtsi file. This patch updates for the same. Reported-by: NSai Pavan Boddu <saipava@xilinx.com> Signed-off-by: NKedareswara rao Appana <appanad@xilinx.com> Signed-off-by: NMichal Simek <michal.simek@xilinx.com>
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由 Michal Simek 提交于
DTC 1.4.2 reports these warnings: Warning (unit_address_vs_reg): Node /amba_apu has a reg or ranges property, but no unit name Warning (unit_address_vs_reg): Node /amba has a reg or ranges property, but no unit name Warning (unit_address_vs_reg): Node /amba/usb@fe200000 has a unit name, but no reg property Warning (unit_address_vs_reg): Node /amba/usb@fe300000 has a unit name, but no reg property Warning (unit_address_vs_reg): Node /amba/dma@fd4c0000/dma-video0channel@fd4c0000 has a unit name, but no reg property Warning (unit_address_vs_reg): Node /amba/dma@fd4c0000/dma-video1channel@fd4c0000 has a unit name, but no reg property Warning (unit_address_vs_reg): Node /amba/dma@fd4c0000/dma-video2channel@fd4c0000 has a unit name, but no reg property Warning (unit_address_vs_reg): Node /amba/dma@fd4c0000/dma-graphicschannel@fd4c0000 has a unit name, but no reg property Warning (unit_address_vs_reg): Node /amba/dma@fd4c0000/dma-audio0channel@fd4c0000 has a unit name, but no reg property Warning (unit_address_vs_reg): Node /amba/dma@fd4c0000/dma-audio1channel@fd4c0000 has a unit name, but no reg property Warning (unit_address_vs_reg): Node /memory has a reg or ranges property, but no unit name This patch is fixing them. Signed-off-by: NMichal Simek <michal.simek@xilinx.com>
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由 Michal Simek 提交于
DTC 1.4.2 reports these warnings: Warning (unit_address_vs_reg): Node /memory has a reg or ranges property, but no unit name Warning (unit_address_vs_reg): Node /pmu has a reg or ranges property, but no unit name Warning (unit_address_vs_reg): Node /fixedregulator@0 has a unit name, but no reg property This patch is fixing them. Signed-off-by: NMichal Simek <michal.simek@xilinx.com>
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Correct the sdhci minimum frequency for ep platform. It should be right shift instead of left shift operand. Signed-off-by: NSiva Durga Prasad Paladugu <sivadur@xilinx.com> Signed-off-by: NMichal Simek <michal.simek@xilinx.com>
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由 Michal Simek 提交于
Autogenerated files contain casting issues and missing function declaration and even usleep implementation. Suppress them for now till these files are fixed. Signed-off-by: NMichal Simek <michal.simek@xilinx.com>
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由 Michal Simek 提交于
Do not setup use_alt bit which copy alternative boot mode to boot mode. The reason is that this bit is cleared after POR but not after any software reset which will cause that after SW reset bootrom will look for different boot image. This patch setups alternative boot mode selection (purely SW handling) and extends code to read this alternative boot mode first and use it if it is setup. Signed-off-by: NMichal Simek <michal.simek@xilinx.com>
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Add support for SD1 with level shifters bootmode. Signed-off-by: NSiva Durga Prasad Paladugu <sivadur@xilinx.com> Signed-off-by: NMichal Simek <michal.simek@xilinx.com>
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由 Michal Simek 提交于
Signed-off-by: NMichal Simek <michal.simek@xilinx.com>
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由 Soren Brinkmann 提交于
The new FW interface returns the IDCODE and version register, leaving extracting bitfields to the caller. Cc: Michal Simek <michal.simek@xilinx.com> Cc: Siva Durga Prasad Paladugu <sivadur@xilinx.com> Signed-off-by: NSoren Brinkmann <soren.brinkmann@xilinx.com> Signed-off-by: NMichal Simek <michal.simek@xilinx.com>
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由 Michal Simek 提交于
Zynq 7000S (Single A9 core) devices is using different ID code. This patch adds this new codes and assign them. Signed-off-by: NMichal Simek <michal.simek@xilinx.com>
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Correct the SGMII enable bit position to 27 instead of 31. Signed-off-by: NSiva Durga Prasad Paladugu <sivadur@xilinx.com> Signed-off-by: NMichal Simek <michal.simek@xilinx.com> Acked-by: NJoe Hershberger <joe.hershberger@ni.com>
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Modify the nwcfg bit definitions to have 32-bit by removing the extra nibble. Signed-off-by: NSiva Durga Prasad Paladugu <sivadur@xilinx.com> Signed-off-by: NMichal Simek <michal.simek@xilinx.com> Acked-by: NJoe Hershberger <joe.hershberger@ni.com>
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Clear ecc ON bit while sending read command as all types of read command(like reading spare) doesnt need ECC to be enabled. It has been anyway taken care in other places whereever required using arasan_nand_enable_ecc(). Signed-off-by: NSiva Durga Prasad Paladugu <sivadur@xilinx.com> Signed-off-by: NMichal Simek <michal.simek@xilinx.com>
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由 Michal Simek 提交于
This patch adds support to check the buswidth on nand flash at runtime based on nand MIO configurations done by FSBL. User needs to correctly configure the MIO's based on the buswidth supported by the nand flash which is present on the board. Added nand8 and nand16 @periph names on slcr driver. Signed-off-by: NJagannadha Sutradharudu Teki <jaganna@xilinx.com> Signed-off-by: NMichal Simek <michal.simek@xilinx.com>
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