- 05 4月, 2016 19 次提交
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由 Michal Simek 提交于
Initial Ceva Sata init code. Signed-off-by: NMichal Simek <michal.simek@xilinx.com> Reviewed-by: NTom Rini <trini@konsulko.com>
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由 Michal Simek 提交于
Handle all Xilinx ZynqMP boards with one fragment. Signed-off-by: NMichal Simek <michal.simek@xilinx.com>
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由 Michal Simek 提交于
Read information about memory from DT. This patch simplify life with synchronization between DT and board files. dram_init() only needs maximum RAM size below 4GB that's why please sort banks in memory node. dram_init_banksize() copies memory setup to bi_dram[]. This will avoid reading information from DT twice. Memory test start/end were changed to DDR location to let memtest still compiled. Signed-off-by: NMichal Simek <michal.simek@xilinx.com>
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由 Michal Simek 提交于
Simplify board config file. Signed-off-by: NMichal Simek <michal.simek@xilinx.com>
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由 Michal Simek 提交于
This option enable adding new platform suport just by adding defconfig and DTS file which will target generic configuration for SoC. Make no sense to extend Kconfig just create a pointer between DTS and configuration file. Signed-off-by: NMichal Simek <michal.simek@xilinx.com>
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由 Michal Simek 提交于
Enabling writing files to FAT and EXT4 for USB. Signed-off-by: NMichal Simek <michal.simek@xilinx.com>
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由 Soren Brinkmann 提交于
Synchronize it with zynq platform. Signed-off-by: NSoren Brinkmann <soren.brinkmann@xilinx.com> Signed-off-by: NMichal Simek <michal.simek@xilinx.com>
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由 Michal Simek 提交于
Do not use debug() when printing error message. Use printf instead. Signed-off-by: NMichal Simek <michal.simek@xilinx.com>
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由 Michal Simek 提交于
OF_CONTROL is enabled by default that's why this is dead code. Signed-off-by: NMichal Simek <michal.simek@xilinx.com>
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由 Michal Simek 提交于
Read information about timer and interrupts from DT. This is the first small step to move timer and intc to DM. Signed-off-by: NMichal Simek <michal.simek@xilinx.com>
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由 Michal Simek 提交于
There is incorrect setting for USB which didn't work with origin ps7_init_gpl.X files. Use default setting for Digilent Zybo projects with HDMI in PL. Signed-off-by: NMichal Simek <monstr@monstr.eu> Signed-off-by: NMichal Simek <michal.simek@xilinx.com>
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由 Michal Simek 提交于
Zybo has on board I2C EEPROM which contains preprogrammed MAC address. Signed-off-by: NMichal Simek <monstr@monstr.eu> Signed-off-by: NMichal Simek <michal.simek@xilinx.com>
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由 Joe Hershberger 提交于
Provide board specific option how to read MAC address from ROM. Do it in generic way to be reusable by differnet boards. If this is not enough board specific functions can be created. Signed-off-by: Joe Hershberger <joe.hershberger@gmail.com> # driver part Signed-off-by: NMichal Simek <monstr@monstr.eu> Signed-off-by: NMichal Simek <michal.simek@xilinx.com>
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由 Michal Simek 提交于
Enable overwriting variables out of main config file. Signed-off-by: NMichal Simek <michal.simek@xilinx.com>
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In SGMII cases the isolate bit might set after DMA and ethernet resets and hence check and clear during setup_phy if it was set. Signed-off-by: NSiva Durga Prasad Paladugu <sivadur@xilinx.com> Acked-by: NJoe Hershberger <joe.hershberger@ni.com> Signed-off-by: NMichal Simek <michal.simek@xilinx.com>
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Pass appropriate interface type to phy_connect instead of zero. Signed-off-by: NSiva Durga Prasad Paladugu <sivadur@xilinx.com> Acked-by: NJoe Hershberger <joe.hershberger@ni.com> Signed-off-by: NMichal Simek <michal.simek@xilinx.com>
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Add support of Xilinx PCS/PMA core phy for Zynq Signed-off-by: NSiva Durga Prasad Paladugu <sivadur@xilinx.com> Signed-off-by: NMichal Simek <michal.simek@xilinx.com>
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Add support of SGMII interface for zynq GEM. Read xlnx,emio property from DT. Signed-off-by: NSiva Durga Prasad Paladugu <sivadur@xilinx.com> Signed-off-by: NMichal Simek <michal.simek@xilinx.com>
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Add phy driver support for xilinx PCS/PMA core Signed-off-by: NSiva Durga Prasad Paladugu <sivadur@xilinx.com> Signed-off-by: NKedareswara rao Appana <appanad@xilinx.com> Signed-off-by: NMichal Simek <michal.simek@xilinx.com>
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- 03 4月, 2016 1 次提交
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由 Karsten Merker 提交于
The RTL8211B_driver structure in drivers/net/phy/realtek.c contains a wrong PHY ID (0x1cc910 instead of 0x1cc912) in the uid field. The lowest four bits of the PHY ID encode the chip revision (B+C/D/E/F) of the RTL8211 and the code originally applied a mask of 0xfffff0 to the PHY ID, so that matching the PHY ID to the appropriate driver code was only done on the chip type (RTL8211), but not on a specific revision. After introduction of support for the RTL8211E, which needed another startup function than the older chip revisions, commit 42205047 changed the mask to 0xffffff to make the chip revision relevant for the match, but didn't provide the now-relevant lower bits of the uid field for the RTL8211B/C. Fix this by setting the full PHY ID in the RTL8211B_driver uid field. Fixes: 42205047 ("net/phy: realtek: Fix the PHY ID mask to ensure the correct Realtek PHY is detected") Signed-off-by: NKarsten Merker <merker@debian.org> Acked-by: NJoe Hershberger <joe.hershberger@ni.com>
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- 02 4月, 2016 20 次提交
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由 Scott Wood 提交于
Freescale is now NXP. I still work there, but I won't be using their mail system for U-Boot development. Signed-off-by: NScott Wood <oss@buserror.net>
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由 Eric Nelson 提交于
Call blk_dread, blk_dwrite, blk_derase to ensure that the block cache is used if enabled and to remove build breakage when CONFIG_BLK is enabled. Signed-off-by: NEric Nelson <eric@nelint.com> Reviewed-by: NTom Rini <trini@konsulko.com>
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由 Eric Nelson 提交于
Call blk_dread, blk_dwrite, blk_derase to ensure that the block cache is used if enabled and to remove build breakage when CONFIG_BLK is enabled. Signed-off-by: NEric Nelson <eric@nelint.com> Reviewed-by: NTom Rini <trini@konsulko.com>
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由 Eric Nelson 提交于
Add a block device cache to speed up repeated reads of block devices by various filesystems. This small amount of cache can dramatically speed up filesystem operations by skipping repeated reads of common areas of a block device (typically directory structures). This has shown to have some benefit on FAT filesystem operations of loading a kernel and RAM disk, but more dramatic benefits on ext4 filesystems when the kernel and/or RAM disk are spread across multiple extent header structures as described in commit fc0fc50f. The cache is implemented through a minimal list (block_cache) maintained in most-recently-used order and count of the current number of entries (cache_count). It uses a maximum block count setting to prevent copies of large block reads and an upper bound on the number of cached areas. The maximum number of entries in the cache defaults to 32 and the maximum number of blocks per cache entry has a default of 2, which has shown to produce the best results on testing of ext4 and FAT filesystems. The 'blkcache' command (enabled through CONFIG_CMD_BLOCK_CACHE) allows changing these values and can be used to tune for a particular filesystem layout. Signed-off-by: NEric Nelson <eric@nelint.com>
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由 Mateusz Kulikowski 提交于
- Update MAINTAINERS - Update git-mailrc Signed-off-by: NMateusz Kulikowski <mateusz.kulikowski@gmail.com> Reviewed-by: NSimon Glass <sjg@chromium.org>
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由 Mateusz Kulikowski 提交于
This commit add support for 96Boards Dragonboard410C. It is board based on APQ8016 Qualcomm SoC, complying with 96boards specification. Features (present out of the box): - 4x Cortex A53 (ARMv8) - 2x USB Host port - 1x USB Device port - 4x LEDs - 1x HDMI connector - 1x uSD connector - 3x buttons (Power, Vol+, Vol-/Reset) - WIFI, Bluetooth with integrated antenna - 8GiB eMMC U-Boot boots chained with fastboot in 64-bit mode. For detailed build instructions see readme.txt in board directory. Signed-off-by: NMateusz Kulikowski <mateusz.kulikowski@gmail.com> Tested-by: NSimon Glass <sjg@chromium.org>
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由 Mateusz Kulikowski 提交于
First supported chip is APQ8016 (that is compatible with MSM8916). Drivers in SoC code: - Reset controller (PSHOLD) - Clock controller (very simple clock configuration for MMC and UART) Signed-off-by: NMateusz Kulikowski <mateusz.kulikowski@gmail.com> Reviewed-by: NSimon Glass <sjg@chromium.org> Tested-by: NSimon Glass <sjg@chromium.org>
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由 Mateusz Kulikowski 提交于
This driver supports GPIOs present on PM8916 PMIC. There are 2 device drivers inside: - GPIO driver (4 "generic" GPIOs) - Keypad driver that presents itself as GPIO with 2 inputs (power and reset) Signed-off-by: NMateusz Kulikowski <mateusz.kulikowski@gmail.com> Reviewed-by: NSimon Glass <sjg@chromium.org> Tested-by: NSimon Glass <sjg@chromium.org>
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由 Mateusz Kulikowski 提交于
This PMIC is connected on SPMI bus so needs SPMI support enabled. Signed-off-by: NMateusz Kulikowski <mateusz.kulikowski@gmail.com> Reviewed-by: NSimon Glass <sjg@chromium.org> Tested-by: NSimon Glass <sjg@chromium.org>
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由 Mateusz Kulikowski 提交于
Support SPMI arbiter on Qualcomm Snapdragon devices. Signed-off-by: NMateusz Kulikowski <mateusz.kulikowski@gmail.com> Reviewed-by: NSimon Glass <sjg@chromium.org> Tested-by: NSimon Glass <sjg@chromium.org>
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由 Mateusz Kulikowski 提交于
This patch adds emulated spmi bus controller with part of pm8916 pmic on it to sandbox and tests validating SPMI uclass. Signed-off-by: NMateusz Kulikowski <mateusz.kulikowski@gmail.com> Reviewed-by: NSimon Glass <sjg@chromium.org>
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由 Mateusz Kulikowski 提交于
Qualcom processors use proprietary bus to talk with PMIC devices - SPMI (System Power Management Interface). On wiring level it is similar to I2C, but on protocol level, it's multi-master and has simple autodetection capabilities. This commit adds simple uclass that provides bus read/write interface. Signed-off-by: NMateusz Kulikowski <mateusz.kulikowski@gmail.com> Reviewed-by: NSimon Glass <sjg@chromium.org> Tested-by: NSimon Glass <sjg@chromium.org>
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由 Mateusz Kulikowski 提交于
This driver is able to reconfigure OTG controller into HOST mode. Board can add board-specific initialization as board_prepare_usb(). It requires USB_ULPI_VIEWPORT enabled in board configuration. Signed-off-by: NMateusz Kulikowski <mateusz.kulikowski@gmail.com> Acked-by: NMarek Vasut <marex@denx.de> Tested-by: NSimon Glass <sjg@chromium.org>
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由 Mateusz Kulikowski 提交于
Use definitions from ehci.h instead. Signed-off-by: NMateusz Kulikowski <mateusz.kulikowski@gmail.com> Acked-by: NMarek Vasut <marex@denx.de> Tested-by: NSimon Glass <sjg@chromium.org>
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由 Mateusz Kulikowski 提交于
Some registers of usb_ehci were marked as reserved. This may be true for some variants of Chipidea USB core, but they have meaning on other devices. The following registers were added: sbusstatus/sbusmode: AHB-related registers genconfig*: Auxiluary IP core configuration registers. Signed-off-by: NMateusz Kulikowski <mateusz.kulikowski@gmail.com> Reviewed-by: NMarek Vasut <marex@denx.de> Tested-by: NSimon Glass <sjg@chromium.org>
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由 Mateusz Kulikowski 提交于
Most of ehci-fsl header describe USB controller designed by Chipidea and used by various SoC vendors. This patch renames it to a generic header: ehci-ci.h Contents of file are not changed (so it contains several references to freescale SoCs). Signed-off-by: NMateusz Kulikowski <mateusz.kulikowski@gmail.com> Acked-by: NMarek Vasut <marex@denx.de> Tested-by: NSimon Glass <sjg@chromium.org>
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由 Mateusz Kulikowski 提交于
Debug printf used '%u' to print size_t variable. This caused warnings on 64-bit machines. Signed-off-by: NMateusz Kulikowski <mateusz.kulikowski@gmail.com> Acked-by: NMarek Vasut <marex@denx.de> Acked-by: NJoe Hershberger <joe.hershberger@ni.com>
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由 Mateusz Kulikowski 提交于
ulpi_read and ulpi_write are used to read/write registers via ULPI bus. Code generates compilation warnings on 64-bit machines where pointer is cast to u32. This patch drops all but last 8 bits of register address. It is possible, because addresses on ULPI bus are 6- or 8-bit. It is not possible (according to ULPI 1.1 spec) to have more than 8-bit addressing. This patch should not cause regressions as all calls to ulpi_read/write use either structure pointer (@ address 0) or integer offsets cast to pointer - addresses requested are way below 8-bit range. Signed-off-by: NMateusz Kulikowski <mateusz.kulikowski@gmail.com> Acked-by: NMarek Vasut <marex@denx.de>
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由 Mateusz Kulikowski 提交于
viewport_addr is address of memory mapped ULPI viewport. It is used only as argument to readl/writel later causing compile warnings on 64-bit devices. This fix changes its type to match pointer size. Signed-off-by: NMateusz Kulikowski <mateusz.kulikowski@gmail.com> Acked-by: NMarek Vasut <marex@denx.de>
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由 Mateusz Kulikowski 提交于
Move CONFIG_USB_ULPI* from headers to defconfigs for boards that use it. Also - add CONFIG_USB where necesarry - all boards use it, but some are not defining it explicitly. Affected boards: colibri_t20, harmony, mcx, mt_ventoux, twister, zynq_(picozed, zc702, zc706, zed, zybo) Signed-off-by: NMateusz Kulikowski <mateusz.kulikowski@gmail.com> Reviewed-by: NSimon Glass <sjg@chromium.org>
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