Signed-off-by: NMasahiro Yamada <yamada.masahiro@socionext.com>

Eliminate the "ph1"_ prefixes from function names because "uniphier_"
describes the SoC familiy better.
Signed-off-by: NMasahiro Yamada <yamada.masahiro@socionext.com>

Signed-off-by: NMasahiro Yamada <yamada.masahiro@socionext.com>

On PH1-sLD3, eMMC and NAND are assigned to different I/O pins.
Both devices can be enabled at the same time.
Signed-off-by: NMasahiro Yamada <yamada.masahiro@socionext.com>

Currently, these functions assume #address-cells and #size-cells are
both one.  Fix them to support 64bit DTB.

Also, I am fixing a buffer overrun bug while I am here.  The array
size of gd->bd->bd_dram is CONFIG_NR_DRAM_BANKS.  The number of
iteration in the loop should be limited by that CONFIG.
Signed-off-by: NMasahiro Yamada <yamada.masahiro@socionext.com>

These defined were used for pre-DM ns16550 serial driver.  They are
unneeded because UniPhier SoCs now use DM serial.
Signed-off-by: NMasahiro Yamada <yamada.masahiro@socionext.com>

This will be used to set up pin-muxing for the NAND controller.
Signed-off-by: NMasahiro Yamada <yamada.masahiro@socionext.com>

Since no clock driver is implemented for peripherals in U-Boot yet,
this property is needed for the serial driver to set up the divisor
register.
Signed-off-by: NMasahiro Yamada <yamada.masahiro@socionext.com>

The pinmux of PH1-LD11 is almost a subset of that of PH1-LD20
(as far as used in boot-loader), so this commit makes the driver
shared between the two SoCs.
Signed-off-by: NMasahiro Yamada <yamada.masahiro@socionext.com>

Add pin configuration and pinmux support for UniPhier PH1-LD20 SoC.
Signed-off-by: NMasahiro Yamada <yamada.masahiro@socionext.com>

Upcoming new pinctrl drivers for PH1-LD11 and PH-LD20 support input
signal gating for each pin.  (While, existing ones only support it
per pin-group.)  This commit prepares the core part for that.
Signed-off-by: NMasahiro Yamada <yamada.masahiro@socionext.com>

The core part of the UniPhier pinctrl driver needs to support a new
capability for upcoming UniPhier ARMv8 SoCs.  This sometimes happens
because pinctrl drivers include really SoC-specific stuff.

This commit intends to tidy up SoC-specific parameters of the existing
drivers before adding new ones.  Having flags would be better than
adding new members every time a new SoC-specific capability comes up.

At this time, there is one flag, UNIPHIER_PINCTRL_CAPS_DBGMUX_SEPARATE.
This capability (I'd say rather quirk) was added for PH1-Pro4 and
PH1-Pro5 as requirement from our customer.  For those SoCs, one pin-mux
setting is controlled by the combination of two separate registers; the
LSB bits at register offset (8 * N) and the MSB bits at (8 * N + 4).
Because it is impossible to update two separate registers atomically,
the LOAD_PINCTRL register should be set in order to make the pin-mux
settings really effective.
Signed-off-by: NMasahiro Yamada <yamada.masahiro@socionext.com>

Currently, fdtdec_get_addr_size() does not support the address
translation, so it cannot handle device trees with non-straight
"ranges" properties.  (This would be a problem with DTS for UniPhier
ARMv8 SoCs.)
Signed-off-by: NMasahiro Yamada <yamada.masahiro@socionext.com>

Currently, fdtdec_get_addr_size() does not support the address
translation, so it cannot handle device trees with non-straight
"ranges" properties.  (This would be a problem with DTS for UniPhier
ARMv8 SoCs.)
Signed-off-by: NMasahiro Yamada <yamada.masahiro@socionext.com>

Currently, fdtdec_get_addr_size() does not support the address
translation, so it cannot handle device trees with non-straight
"ranges" properties.  (This would be a problem with DTS for UniPhier
ARMv8 SoCs.)
Signed-off-by: NMasahiro Yamada <yamada.masahiro@socionext.com>

Currently, fdtdec_get_addr_size() does not support the address
translation, so it cannot handle device trees with non-straight
"ranges" properties.  (This would be a problem with DTS for UniPhier
ARMv8 SoCs.)
Signed-off-by: NMasahiro Yamada <yamada.masahiro@socionext.com>

Currently, fdtdec_get_addr_size() does not support the address
translation, so it cannot handle device trees with non-straight
"ranges" properties.  (This would be a problem with DTS for UniPhier
ARMv8 SoCs.)
Signed-off-by: NMasahiro Yamada <yamada.masahiro@socionext.com>

Currently, fdtdec_get_addr_size() does not support the address
translation, so it cannot handle device trees with non-straight
"ranges" properties.  (This would be a problem with DTS for UniPhier
ARMv8 SoCs.)
Signed-off-by: NMasahiro Yamada <yamada.masahiro@socionext.com>

This command would be useful to update U-Boot images in SRAM.
Signed-off-by: NMasahiro Yamada <yamada.masahiro@socionext.com>

Commit d085ecd6 ("ARM: uniphier: switch to raw U-Boot image")
claimed that u-boot-with-spl.bin would be useful in its commit log,
but it was not available because the commit missed to define
CONFIG_SPL_MAX_SIZE.  Without it, CONFIG_SPL_PAD_TO is not defined
either (see include/config_fallbacks.h).  So, the SPL image is not
padded correctly.
Signed-off-by: NMasahiro Yamada <yamada.masahiro@socionext.com>

Read Denali hardware revision number and use it to
calculate max_banks,  The encoding of max_banks changed
in Denali revision 5.1.

[ Linux commit : 271707b1d817f5104e02b2bd1bab43f0c8759418 ]
Signed-off-by: NGraham Moore <grmoore@opensource.altera.com>
[Brian: parentheses around macro arg]
Signed-off-by: NBrian Norris <computersforpeace@gmail.com>
[Masahiro: import from Linux and adjust ioread32() to readl() ]
Signed-off-by: NMasahiro Yamada <yamada.masahiro@socionext.com>

This bit needs to be set for system suspend/resume to work. This setting
will be documented in an updated TRM at some time in the future.
Signed-off-by: NStephen Warren <swarren@nvidia.com>
Signed-off-by: NTom Warren <twarren@nvidia.com>

This patch enable VID support for ls2080ardb platform.
It uses the common VID driver.
Signed-off-by: NRai Harninder <harninder.rai@nxp.com>
Reviewed-by: NYork Sun <york.sun@nxp.com>

Clock phase and polarity for DSPI flash need to be set.
Signed-off-by: NGong Qianyu <Qianyu.Gong@nxp.com>
Reviewed-by: NYork Sun <york.sun@nxp.com>

Signed-off-by: NMingkai Hu <mingkai.hu@nxp.com>
Signed-off-by: NGong Qianyu <Qianyu.Gong@nxp.com>
Reviewed-by: NYork Sun <york.sun@nxp.com>

Signed-off-by: NMingkai Hu <mingkai.hu@nxp.com>
Signed-off-by: NGong Qianyu <Qianyu.Gong@nxp.com>
Reviewed-by: NYork Sun <york.sun@nxp.com>

Use a pointer to pass image address to fsl_secboot_validate(),
instead of using environmental variable "img_addr".
Signed-off-by: NAneesh Bansal <aneesh.bansal@nxp.com>
Signed-off-by: NSaksham Jain <saksham.jain@nxp.com>
Reviewed-by: NYork Sun <york.sun@nxp.com>

In case of fatal failure during secure boot execution (e.g. header
not found), reset is asserted to stop execution. If the RESET_REQ
is not tied to HRESET, this allows the execution to continue.

Add esbh_halt() after the reset to make sure execution stops.
Signed-off-by: NAneesh Bansal <aneesh.bansal@nxp.com>
Signed-off-by: NSaksham Jain <saksham.jain@nxp.com>
Reviewed-by: NYork Sun <york.sun@nxp.com>

For secure boot, currently we were using fixed bootargs for all SoCs.
This is not needed and we can use the bootargs which are used in
non-secure boot.
Signed-off-by: NAneesh Bansal <aneesh.bansal@nxp.com>
Signed-off-by: NSaksham Jain <saksham.jain@nxp.com>
Reviewed-by: NYork Sun <york.sun@nxp.com>

This commit solves CAAM coherency issue on ls2080. When caches are
enabled and CAAM's DMA's AXI transcations are not made cacheable,
Core reads/writes data from/to caches and CAAM does from main memory.
This forces data flushes to synchronize various data structures. But
even if any data in proximity of these structures is read by core,
these structures again are fetched in caches.

To avoid this problem, either all the data that CAAM accesses can be
made cache line aligned or CAAM transcations can be made cacheable.

So, this commit makes CAAM transcations as write back with write and
read allocate.
Signed-off-by: NSaksham Jain <saksham.jain@nxp.com>
Reviewed-by: NYork Sun <york.sun@nxp.com>

When MMU is disabled, 64-bit write must be aligned at 64-bit
boundary. Becaue the memory location is not guaranteed to be 64-bit
aligned, the 64-bit write needs to be split into two 32-bit writes
to avoid the alignment exception.
Signed-off-by: NAneesh Bansal <aneesh.bansal@nxp.com>
Signed-off-by: NSaksham Jain <saksham.jain@nxp.com>
Reviewed-by: NYork Sun <york.sun@nxp.com>

During secure boot, SMMU is enabled on POR by SP bootrom. SMMU needs
to be put in bypass mode in uboot to enable CAAM transcations to pass
through.

For non-secure boot, SP BootROM doesn't enable SMMU, which is in
bypass mode out of reset.
Signed-off-by: NAneesh Bansal <aneesh.bansal@nxp.com>
Signed-off-by: NSaksham Jain <saksham.jain@nxp.com>
Reviewed-by: NYork Sun <york.sun@nxp.com>

The GUR (DCFG) registers in CCSR space are in little endian format.
Define a config CONFIG_SYS_FSL_CCSR_GUR_LE in
arch/arm/include/asm/arch-fsl-layerscape/config.h
Signed-off-by: NAneesh Bansal <aneesh.bansal@nxp.com>
Signed-off-by: NSaksham Jain <saksham.jain@nxp.com>
Reviewed-by: NYork Sun <york.sun@nxp.com>

"fdt_high" env variable was set to 0xcfffffff for secure boot.
Change it to 0xa0000000 for LS2080 to be consistent with non-secure
boot targets.
Signed-off-by: NAneesh Bansal <aneesh.bansal@nxp.com>
Signed-off-by: NSaksham Jain <saksham.jain@nxp.com>
Reviewed-by: NYork Sun <york.sun@nxp.com>

To unify steps for secure boot for xip (eg. NOR) and non-xip memories
(eg. NAND, SD), bootscipts and its header are copied to main memory.
Validation and execution are performed from there.

For other ARM Platforms (ls1043 and ls1020), to avoid disruption of
existing users, this copy step is not used for NOR boot.
Signed-off-by: NAneesh Bansal <aneesh.bansal@nxp.com>
Signed-off-by: NSaksham Jain <saksham.jain@nxp.com>
Reviewed-by: NYork Sun <york.sun@nxp.com>

During secure boot, Linux image along with other images are validated
using bootscript. This bootscript also needs to be validated before
it executes. This requires a header for bootscript.

When secure boot is enabled, default bootcmd is changed to first
validate bootscript using the header and then execute the script.

For ls2080, NOR memory map is different from other ARM SoCs. So a new
address on NOR is used for this bootscript header (0x583920000). The
Bootscript address is mentioned in this header along with addresses of
other images.
Signed-off-by: NAneesh Bansal <aneesh.bansal@nxp.com>
Signed-off-by: NSaksham Jain <saksham.jain@nxp.com>
Reviewed-by: NYork Sun <york.sun@nxp.com>

Sec_init has been called at the beginning to initialize SEC Block
(CAAM) which is used by secure boot validation later for both ls2080a
qds and rdb. 64-bit address in ESBC Header has been enabled. Secure
boot defconfigs are created for boards (NOR boot).
Signed-off-by: NSaksham Jain <saksham.jain@nxp.com>
Reviewed-by: NYork Sun <york.sun@nxp.com>

For secure boot, a header is used to identify key table, signature
and image address. A new header structure is added for lsch3.

Currently key extension (IE) feature is not supported. Single key
feature is not supported. Keys must be in table format. Hence, SRK
(key table) must be present. Max key number has increase from 4 to
8. The 8th key is irrevocable. A new barker Code is used.
Signed-off-by: NAneesh Bansal <aneesh.bansal@nxp.com>
Signed-off-by: NSaksham Jain <saksham.jain@nxp.com>
Reviewed-by: NYork Sun <york.sun@nxp.com>