Added support to load partial bitstreams.
The partial bitstreams can be loaded using the below commands
Commands:
fpga loadp <dev> <addr> <size>
fpga loadbp <dev> <addr> <size>
The full bit streams can be loaded using the
old commands(fpga load and fpga loadb).
Signed-off-by: NSiva Durga Prasad Paladugu <sivadur@xilinx.com>
Signed-off-by: NMichal Simek <michal.simek@xilinx.com>

Clean up partial, full and compressed bitstream handling.
U-Boot supports full bitstream loading and partial
based on detection which is not 100% correct.
Extending fpga_load/fpga_loadbitstream() with one more
argument which stores bitstream type.
Signed-off-by: NMichal Simek <michal.simek@xilinx.com>

Guard the LOADMK functionality with config to provide
an option to enable or disable it.
Enable it for all platforms in mainline which enable CONFIG_CMD_FPGA.
Signed-off-by: NSiva Durga Prasad Paladugu <sivadur@xilinx.com>
Signed-off-by: NMichal Simek <michal.simek@xilinx.com>

Fix typo in CMD_FPGA command enabling.
Signed-off-by: NMichal Simek <michal.simek@xilinx.com>

The new 768KB u-boot image size requires changes for
SRIO/PCIE boot. These addresses need to be updated to
appropriate locations.

The updated addresses are used to configure the SRIO/PCIE
inbound windows for the boot, and they must be aligned
with the window size based on the SRIO/PCIE modules requirement.
So for the 768KB u-boot image, the inbound window cannot be set
with 0xfff40000 base address and 0xc0000 size, it should be
extended to 1MB size and the base address can be aligned with
the size.
Signed-off-by: NLiu Gang <Gang.Liu@freescale.com>
Reviewed-by: NYork Sun <yorksun@freescale.com>

AFAICT, c=ffe does nothing and was a typo from the original commit
d1712369 "powerpc/p4080: Add support
for the P4080DS board" and just kept on getting duplicated
in subsequently added board config files.
Signed-off-by: NKim Phillips <kim.phillips@freescale.com>
Acked-by: NEdward Swarthout <ed.swarthout@freescale.com>
Reviewed-by: NYork Sun <yorksun@freescale.com>

In the earlier patches, the SPL/TPL fraamework was introduced.
For SD/SPI flash booting way, we introduce the SPL to enable a loader stub. The
SPL was loaded by the code from the internal on-chip ROM. The SPL initializes
the DDR according to the SPD and loads the final uboot image into DDR, then
jump to the DDR to begin execution.

For NAND booting way, the nand SPL has size limitation on some board(e.g.
P1010RDB), it can not be more than 4KB, we can call it "minimal SPL", So the
dynamic DDR driver doesn't fit into this minimum SPL. We added the TPL that is
loaded by the the minimal SPL. The TPL initializes the DDR according to the SPD
and loads the final uboot image into DDR,then jump to the DDR to begin execution.

This patch enabled SPL/TPL for P1_P2_RDB to support starting from NAND/SD/SPI
flash with SPL framework and initializing the DDR according to SPD in the SPL/TPL.
Because the minimal SPL load the TPL to L2 SRAM and the jump to the L2 SRAM to
execute, so the section .resetvec is no longer needed.
Signed-off-by: NPrabhakar Kushwaha <prabhakar@freescale.com>
Reviewed-by: NYork Sun <yorksun@freescale.com>

In case of secure boot from NAND, CSPR and FTIM settings are
same as non-secure NAND boot. CSPR0 is configured as NAND and
CSPR1 is configured as NOR.
Signed-off-by: NAneesh Bansal <aneesh.bansal@freescale.com>
Reviewed-by: NYork Sun <yorksun@freescale.com>

P1020 SoC which has two USB controllers, but only first one is used
on this platform.
Signed-off-by: NRamneek Mehresh <ramneek.mehresh@freescale.com>
Reviewed-by: NYork Sun <yorksun@freescale.com>

Define and use CONTROL_REGISTER_W1C_MASK to make sure that
w1c bits of usb control register do not get reset while
writing any other bit
Signed-off-by: NNikhil Badola <nikhil.badola@freescale.com>
Signed-off-by: NRamneek Mehresh <ramneek.mehresh@freescale.com>
Reviewed-by: NYork Sun <yorksun@freescale.com>

B4460 differs from B4860 only in number of CPU cores,
hence used existing support for B4860.
B4460 has 2 PPC cores whereas B4860 has 4 PPC cores.
Signed-off-by: NShaveta Leekha <shaveta@freescale.com>
Signed-off-by: NSandeep Singh <Sandeep@freescale.com>
Signed-off-by: NPoonam Aggrwal <poonam.aggrwal@freescale.com>
Reviewed-by: NYork Sun <yorksun@freescale.com>

T4160RDB shares the same platform as T4240RDB. T4160 is
a low power version of T4240, with the eight e6500 cores,
two DDR3 controllers, and same peripheral bus interfaces.
Signed-off-by: NChunhe Lan <Chunhe.Lan@freescale.com>
Reviewed-by: NYork Sun <yorksun@freescale.com>

By default, all PEX inbound windows PEX_PEXIWARn[TRGT] are
mapped to 0xF, which is local memory. But for BSC9132, 0xF
is CCSR, 0x0 is local memory.
Signed-off-by: NMinghuan Lian <Minghuan.Lian@freescale.com>
Signed-off-by: NChunhe Lan <Chunhe.Lan@freescale.com>
Reviewed-by: NYork Sun <yorksun@freescale.com>

T104xrdb has several sleep management signals that are used for deep
sleep. They are enabled by OS to enter deep sleep and should be
disabled by u-boot when cores wake up.
Signed-off-by: NTang Yuantian <Yuantian.Tang@freescale.com>
Reviewed-by: NYork Sun <yorksun@freescale.com>

According to AN3638, CRC of NXID v1 is at the end of the
256-byte I2C memory. The wrong CRC32 offset prevents Uboot
from reading system information from EEPROM. No NXID v0 is
being used on Freescale boards.
Signed-off-by: NEbony Zhu <b45385@freescale.com>
Reviewed-by: NYork Sun <yorksun@freescale.com>

This patch adds support for VSC8664 PHY module which can
be found on Freescale's T4240RDB boards.
Signed-off-by: NChunhe Lan <Chunhe.Lan@freescale.com>
Reviewed-by: NYork Sun <yorksun@freescale.com>

There is an unfortunate bug in the signoff suppression logic. The first
pass is performed with 'git log', and all signoffs are added to the
supression set, such that the second time (when processing the real
patches) we always suppress the signoffs.

Correct this by only suppressing signoffs in the second pass.
Signed-off-by: NSimon Glass <sjg@chromium.org>
Tested-by: NMichal Simek <monstr@monstr.eu>
Tested-by: NAndreas Bießmann <andreas.devel@googlemail.com>

Because sandbox is not a real hardware, setting vendor=sandbox is
almost meaningless.

This commit sets sandbox's vendor field to '-'.

It is a good thing that it decreases one level directory hierarchy.
The files board/sandbox/sandbox/* have been moved to board/sandbox/*.
Signed-off-by: NMasahiro Yamada <yamada.m@jp.panasonic.com>
Acked-by: NSimon Glass <sjg@chromium.org>
Tested-by: NSimon Glass <sjg@chromium.org>

This reverts commit 25806090.

Conflicts:
	boards.cfg

Wrong patch 25806090 was applied by accident. Revert it.
Signed-off-by: NMasahiro Yamada <yamada.m@jp.panasonic.com>
Cc: Simon Glass <sjg@chromium.org>
Acked-by: NSimon Glass <sjg@chromium.org>

These are used only once, so their is no need to have them global.

This also stops mvtwsi from using any bss vars making it easier to use
before dram init (to talk to the pmic to set the dram voltage).
Signed-off-by: NHans de Goede <hdegoede@redhat.com>

The TWSI_FREQUENCY macro was wrong in 2 ways:
1) It was casting the result of the calculations to an u8, while i2c clk
rates are often >= 100Khz which won't fit in a u8, drop the cast.
2) It had an extra factor of 2 in the divider which neither the datasheet nor
the Linux driver have.

The comment for the default value was wrongly saying that m lives in
bits 4-7, while in reality it is in bits 3-6, as can be seen from the correct
shift by 3 used in i2c_init().

While at it remove the unused twsi_actual_speed variable.
Signed-off-by: NHans de Goede <hdegoede@redhat.com>

"make ep8248_config" fails with an error like this:

    $ make ep8248_config
    make: *** [ep8248_config] Error 1

Its cause is that there are two entries for "ep8248".

The first is around line 652 of boards.cfg. (as Active)

The second appears around line 1230. (as Orphan)

This bug was accidentally introduced by commit e7e90901.
But it is not the author's fault. He just intended to change
IDS8247 board.

The commiter added ep8248 entry by mistake when he resolved a conflict.
Signed-off-by: NMasahiro Yamada <yamada.m@jp.panasonic.com>
Cc: Heiko Schocher <hs@denx.de>
Cc: Kim Phillips <kim.phillips@linaro.org>
Acked-by: NHeiko Schocher <hs@denx.de>
Acked-by: NKim Phillips <kim.phillips@freescale.com>

This patch converts the following boards to use generic board: MPC8536DS,
MPC8572DS, MPC8641HPCN, p1_p2_rdb_pc, corenet_ds, t4qds, B4860QDS. It has
been tested on NOR boot on MPC8536DS, MPC8572DS, P1021RDB, P4080DS,
P5020DS, P5040DS, P3041DS, T4240QDS, B4860QDS.
Signed-off-by: NYork Sun <yorksun@freescale.com>
CC: Ying Zhang <b40530@freescale.com>
CC: Prabhakar Kushwaha <prabhakar@freescale.com>
CC: Haijun.Zhang <Haijun.Zhang@freescale.com>
CC: Scott Wood <scottwood@freescale.com>
CC: Shaohui Xie <Shaohui.Xie@freescale.com>

The argument boot_flag of board_inti_f() hasn't been used for powerpc until
recent changing to use generic board. Set it to 0 as a proper value.
Signed-off-by: NYork Sun <yorksun@freescale.com>

baord_init_f takes one argument, boot_flag. It has not been used for
powerpc, until recently changing to use generic board architecture.
The boot flag is added as a return value from cpu_init_f().
Signed-off-by: NYork Sun <yorksun@freescale.com>
CC: Alexander Graf <agraf@suse.de>

The return value has not been checked by its caller, until recent change
of using generic board architecture. The error of this function is not
critical enough to hang the system. Printing the warning message is enough
to catch user's attention. U-boot should continue to boot to give user
a chance to fix the EEPROM. Chaning the return value to 0 to avoid hanging
in the board_init_r().
Signed-off-by: NYork Sun <yorksun@freescale.com>

The pointer of device tree comes from r3 for QEMU. This is not the case
for normal SoCs out of reset. Having gd->fdt_blob as 0 is important for
other functions to detect the non-existence of device tree.
Signed-off-by: NYork Sun <yorksun@freescale.com>
CC: Alexander Graf <agraf@suse.de>

U-boot image has grown and exceeded the predefined 512KB. Increasing to
768KB to align with other powerpc boards. Tested on MPC8572DS for 32-
and 36-bit targets with NOR flash boot. NAND boot is not covered by
this patch.

Also update board maintainer for these boards.
Signed-off-by: NYork Sun <yorksun@freescale.com>
Acked-by: NHeiko Schocher <hs@denx.de>

when qe-ucode fails to be uploaded, "deep sleep" will hang.
if there is no qe-ucode, disable qe module for platforms
which support "deep sleep"
Signed-off-by: NZhao Qiang <B45475@freescale.com>

This patch enables the E500 QEMU board to use the generic cross-arch board
infrastructure.
Signed-off-by: NAlexander Graf <agraf@suse.de>

We want to use the TLB mapping helpers in relocated mode as well. These helpers
need to have awareness of already occupied TLB entries. We already had them in
sync in non-relocated mode, but need to resync them when we move into relocated.
Signed-off-by: NAlexander Graf <agraf@suse.de>

For the QEMU machine type, we can plug in either e500v2, e500mc, e5500
or e6500 style cores into the system. U-boot has to work with all of them.

So avoid using HID1 which is not available on e500mc systems to make sure
we don't trap on it.
Signed-off-by: NAlexander Graf <agraf@suse.de>

We only need u-boot to bother about a single core in the QEMU machine.
Everything that would require additional knowledge of more cores gets
handled by QEMU and passed straight into the payload we execute.

Because of this setup, it would be counterproductive to enable SMP support
in u-boot. We would have to rip CPUs out of already existing spin tables
and respin them from u-boot. It would be a pretty big mess.

So only assume we have a single core. This fixes errors about CONFIG_MP
being disabled.
Signed-off-by: NAlexander Graf <agraf@suse.de>

Signed-off-by: NValentin Longchamp <valentin.longchamp@keymile.com>

This should prevent the problems that the CCF can deadlock with certain
traffic patterns.

This also fixes the workaround for A-006559 that was not correctly
implemented before.
Signed-off-by: NValentin Longchamp <valentin.longchamp@keymile.com>

Fix the IRQ/GPIO settings: all the muxed GPIO/external IRQs that are
used as internal interrupts are defined as GPIOs to avoid confusion
between the internal/external interrupts.
Signed-off-by: NValentin Longchamp <valentin.longchamp@keymile.com>

This adds the reset support for the following devices that was until
then not implemented:
- BFTIC4
- QSFPs

This also fixes the configuration of the prst behaviour for the other
resets: Only the u-boot and kernel relevant subsystems are taken out of
reset (pcie, ZL30158, and front eth phy).

Most of the prst config move to misc_init_f(), except for the PCIe
related ones that are in pci_init_board and the bftic and ZL30158 ones
that should be done as soon as possible.

Only the behavior of the Hooper reset is changed according to the
documentation as the application is not able to not configure the switch
when it is not reset.
Signed-off-by: NValentin Longchamp <valentin.longchamp@keymile.com>

This prevents u-boot from accessing into the reserved memory areas that
we have for /var and the logbooks.
Signed-off-by: NValentin Longchamp <valentin.longchamp@keymile.com>