"Superfloppy" format (in U-Boot called PBR) did not work for FAT32 as
the file system type string is at a different location. Add support
for FAT32.
Signed-off-by: NWolfgang Denk <wd@denx.de>

The device type was left uninitialized which caused later tests
against DEV_TYPE_UNKNOWN to fail. In the result, "usb part" would
attempt to print information about non-existent devices like this:

	=> usb part
	print_part of 0

	Partition Map for USB device 0  --   Partition Type: DOS

	Partition     Start Sector     Num Sectors     Type
	    1                    0         2031616      f8

	print_part of 1
	## Unknown partition table

	print_part of 2
	## Unknown partition table

	print_part of 3
	## Unknown partition table

	print_part of 4
	## Unknown partition table
	=>

By initializing the type as DEV_TYPE_UNKNOWN we avoid all the
"Unknown partition table" messages.

[Note: the "print_part of ?" messages is left over debug code that
will be removed in another patch.]
Signed-off-by: NWolfgang Denk <wd@denx.de>
Cc: Remy Bohmer <linux@bohmer.net>

Lots of code use this construct:

	cmd_usage(cmdtp);
	return 1;

Change cmd_usage() let it return 1 - then we can replace all these
ocurrances by

	return cmd_usage(cmdtp);

This fixes a few places with incorrect return code handling, too.
Signed-off-by: NWolfgang Denk <wd@denx.de>

Signed-off-by: NStefan Roese <sr@denx.de>

Signed-off-by: NStefan Roese <sr@denx.de>

Signed-off-by: NStefan Roese <sr@denx.de>

This patch adds the "ecctest" command to test and simulate ECC errors
(single bit and/or double bit) while running from SDRAM. Currently only
the IBM DDR2 controller is supported (405EX, 440SP(e), 460EX/GT).

This is done by copying and calling functions, modifying the SDRAM
controller operation mode, in internal SRAM/OCM.

For correctable ECC errors (single bit) only the status will be printed
since the DDR2 controller doesn't provide the faulting address:

=> ecctest 1000000 1
Using address 01000000 for 1 bit ECC error injection
ECC: Correctable error

Uncorrectable ECC errors (double bit) will also display the faulting
address:

=> ecctest 1000000 2
Using address 01000000 for 2 bit ECC error injection
ECC: Uncorrectable error at 0x0001000000

To enable this "ecctest" function you need to define CONFIG_CMD_ECCTEST
in the board config header.

Tested on katmai and t3corp.
Signed-off-by: NStefan Roese <sr@denx.de>

Use the correct macro instead of the hardcoded 0x4c to clear the ECC
status in the 440/460 DDR(2) error status register after ECC
initialization.

Also the non-440 parts (405EX(r) right now) and the IBM DDR PPC variants
(440GX) use a different registers to clear this error status. Use the
correct ones.
Signed-off-by: NStefan Roese <sr@denx.de>

Make sure that some SDRAM/DDR2 registers are only defined for the PPC
variants really implementing those registers.
Signed-off-by: NStefan Roese <sr@denx.de>

Using this define, a board can define an opimized RFDC value and use
the auto calibration code to "tune" the remaining DDR2 controller
calibration register.
Signed-off-by: NStefan Roese <sr@denx.de>

This patch fixes some problems for the T3CORP board. Here the list
of the changes:

- Add 600-67 and 677 CPU frequency setting to chip_config
  command
- Define CONFIG_DDR_RFDC_FIXED on t3corp:
  While using the "normal" auto calibration code, sometimes values for
  RFDC were picked (>= T3) that resulted in a non-working U-Boot (hang
  upon relocation, while running from SDRAM). With this optimized RFDC
  value we can force this register and use the auto-calibration code to
  setup the remaining calibration registers.
- Increase sizes of FPGA chips selects
- EBC timing updated OEN=3 for 66 MHz EBC speed
- Change ext. IRQ2 setup to level-low active
- Enable CONFIG_SYS_CFI_FLASH_STATUS_POLL

By defining CONFIG_SYS_CFI_FLASH_STATUS_POLL, DQ7 is polled to detect the
chip busy status. This is now used instead of the data toggle method which
is used historically by default in the common CFI driver. With this change
a problem with not written data is solved on this board, where a 32 byte
block of data is still erased instead of filled with the correct content
after these commands:

=> erase 0xfc100000 +0x1000000

....................................................................
done
Erased 128 sectors
=> cp.b 0x100000 0xfc100000 0x1000000
Copy to Flash... done
=> cmp.b 0x100000 0xfc100000 0x1000000
byte at 0x00d0d6c0 (0x00) != byte at 0xfcd0d6c0 (0xff)
Total of 12637888 bytes were the same
Signed-off-by: NStefan Roese <sr@denx.de>

Functions added to support board callbacks for USB init. This
isolates USB manipulations such that it is only touched if USB is
used by U-Boot.
Signed-off-by: NDave Mitchell <dmitchell@appliedmicro.com>
Signed-off-by: NRupjyoti Sarmah <rsarmah@appliedmicro.com>
Signed-off-by: NStefan Roese <sr@denx.de>

Since the vast majority of GPIO I2C implementations behave the same way,
support the common GPIO framework with default settings.

This adds two new defines CONFIG_SOFT_I2C_GPIO_{SCL,SDA} so that boards
which want GPIO I2C support need only define these.
Signed-off-by: NMike Frysinger <vapier@gentoo.org>
Tested-by: NThomas Chou <thomas@wytron.com.tw>

Move serdes init until after we are in ram so we can keep track of a
global static protocal map for the particular serdes config we are in.
This makes is_serdes_configured() much simplier and not constantly
reading registers to determine if a given device is enabled based on the
protocol.
Signed-off-by: NKumar Gala <galak@kernel.crashing.org>

Move serdes init until after we are in ram so we can keep track of a
global static protocal map for the particular serdes config we are in.
This makes is_serdes_configured() much simplier and not constantly
reading registers to determine if a given device is enabled based on the
protocol.
Signed-off-by: NKumar Gala <galak@kernel.crashing.org>

There are various locations that we have chip specific info:

* Makefile for which ddr code to build
* Added p3041 to cpu_type_list and SVR list
* Added number of LAWs for p3041
* Set CONFIG_MAX_CPUS to 4 for p3041
Signed-off-by: NKumar Gala <galak@kernel.crashing.org>

There are various locations that we have chip specific info:

* Makefile for which ddr code to build
* Added p5020 & p5010 to cpu_type_list and SVR list
* Added number of LAWs for p5020
* Set CONFIG_MAX_CPUS to 2 for p5020
Signed-off-by: NKumar Gala <galak@kernel.crashing.org>

The user manual refers to FMAN1 and FMAN2 not 0 and 1.
Signed-off-by: NEmil Medve <Emilian.Medve@Freescale.com>
Signed-off-by: NKumar Gala <galak@kernel.crashing.org>

On QorIQ CoreNet based devices we have a global clocking block.  We want
to keep track of SYSCLK frequency as it is what is used to derive all
other frequencies in the SoC
Signed-off-by: NKumar Gala <galak@kernel.crashing.org>

Move to using fdt_node_offset_by_compat_reg to find the node offsets we
want to update instead of using aliases.
Signed-off-by: NKumar Gala <galak@kernel.crashing.org>

Previously we used an alias the pci node to determine which node to
fixup or delete.  Now we use the new fdt_node_offset_by_compat_reg to
find the node to update.

Additionally, we replace the code in each board with a single macro call
that makes assumes uniform naming and reduces duplication in this area.
Signed-off-by: NKumar Gala <galak@kernel.crashing.org>

Given a compatible string and physical address try and find a node that
matches.  This is useful when we want to find a specific device node to
update (for example if we have multiple PCI nodes we can use the
physical address to distinguish them when trying to update the device
tree).
Signed-off-by: NKumar Gala <galak@kernel.crashing.org>
Acked-by: NGerald Van Baren <vanbaren@cideas.com>

This code is extracted out of the Linux Kernel code from
arch/powerpc/kernel/prom_parse.c.

We maintain some of the same structure to support multiple bus types even
though we only have one in the current code.  In the future we might want
to translate across a PCI bus and thus it will be easier to add that
functionality back in.
Signed-off-by: NKumar Gala <galak@kernel.crashing.org>
Acked-by: NGerald Van Baren <vanbaren@cideas.com>

The MPC8641 boards actually only have PCIE not PCI.  Rename so we are
uniform with regards to names so we can replace this code with templated
code.
Signed-off-by: NKumar Gala <galak@kernel.crashing.org>

Remove dupliacted setting of PCI/PCIe address and offsets in board
config.h.  Renamed CONFIG_SYS_PCI1/2_ADDR to CONFIG_SYS_PCI1/2ADDR on
MPC8641 boards since its really PCIE controllers and not PCI.
Signed-off-by: NKumar Gala <galak@kernel.crashing.org>

Remove dupliacted setting of PCI/PCIe address and offsets in board
config.h.
Signed-off-by: NKumar Gala <galak@kernel.crashing.org>

The board maintainer states:

    The GTH board is obsolete and has not been manufactured for
    several years.
    To my knowledge, no recent U-Boot build has been tested on that
    card.

So drop support for this board.
Signed-off-by: NWolfgang Denk <wd@denx.de>
Cc: Thomas Lange <thomas@corelatus.se>
Acked-by: Thomas Lange<thomas@corelatus.se>

Signed-off-by: NAnatolij Gustschin <agust@denx.de>

The code to map SERDES configs to slot names is board specific and not
chip specific.  Thus it should live in board/freescale/p1022ds/ and not
in arch/powerpc/cpu/.
Signed-off-by: NKumar Gala <galak@kernel.crashing.org>

Signed-off-by: NKumar Gala <galak@kernel.crashing.org>

Signed-off-by: NKumar Gala <galak@kernel.crashing.org>

Add 'errata' command to report what errata we workaround.  Report
workaround for erratum SATA-A001 on P1022/P1013.

Also sorted the CONFIG_CMD_* list.
Signed-off-by: NKumar Gala <galak@kernel.crashing.org>