This is a low-cost ARMv8 SoC from Socionext Inc.
Signed-off-by: NMasahiro Yamada <yamada.masahiro@socionext.com>

Correct some register names.
Signed-off-by: NMasahiro Yamada <yamada.masahiro@socionext.com>

This header will be shared between PH1-LD11 and PH1-LD20
(and hopefully new ARMv8 SoCs developed in the future),
so umc64-regs.h would be a better fit.
Signed-off-by: NMasahiro Yamada <yamada.masahiro@socionext.com>

Tidy up alignment of open parentheses.
Signed-off-by: NMasahiro Yamada <yamada.masahiro@socionext.com>

The Boot ROM has enabled D-cache and MMU setting DDR memory area
as Normal Memory in its page table.  Disable D-cache and MMU
before jumping to U-Boot proper.
Signed-off-by: NMasahiro Yamada <yamada.masahiro@socionext.com>

Signed-off-by: NTom Rini <trini@konsulko.com>

Conflicts:
	drivers/net/zynq_gem.c

The code assumed that if the interface is not RGMII configured
then it must be SGMII configured.  This device has the ability
to support most of the MII interfaces.  Therefore add the
helper for SGMII and only configure the device if the interface is
configured for SGMII.
Signed-off-by: NDan Murphy <dmurphy@ti.com>
Reviewed-by: NMugunthan V N <mugunthanvnm@ti.com>
Reviewed-by: NMichal Simek <michal.simek@xilinx.com>
Acked-by: NJoe Hershberger <joe.hershberger@ni.com>

Add a helper to phy.h to identify whether the
phy is configured for SGMII all variables.
Signed-off-by: NDan Murphy <dmurphy@ti.com>
Reviewed-by: NMugunthan V N <mugunthanvnm@ti.com>
Reviewed-by: NMichal Simek <michal.simek@xilinx.com>
Tested-by: NMugunthan V N <mugunthanvnm@ti.com>
Acked-by: NJoe Hershberger <joe.hershberger@ni.com>

Move the phy_interface_is_rgmii to the phy.h
file for all phy's to be able to use the API.

This now aligns with the Linux kernel based on
commit e463d88c36d42211aa72ed76d32fb8bf37820ef1
Signed-off-by: NDan Murphy <dmurphy@ti.com>
Reviewed-by: NMugunthan V N <mugunthanvnm@ti.com>
Reviewed-by: NMichal Simek <michal.simek@xilinx.com>
Tested-by: NMugunthan V N <mugunthanvnm@ti.com>
Acked-by: NJoe Hershberger <joe.hershberger@ni.com>

Not all devices use the same internal delay or fifo depth.
Add the ability to set the internal delay for rx or tx and the
fifo depth via the devicetree.  If the value is not set in the
devicetree then set the delay to the default.

If devicetree is not used then use the default defines within the
driver.
Signed-off-by: NDan Murphy <dmurphy@ti.com>
Tested-by: NMugunthan V N <mugunthanvnm@ti.com>
Acked-by: NJoe Hershberger <joe.hershberger@ni.com>

Add the device tree bindings and the accompanying documentation
for the TI DP83867 Giga bit ethernet phy driver.

The original document was from:
    [commit 2a10154abcb75ad0d7b6bfea6210ac743ec60897 from the Linux kernel]
Signed-off-by: NDan Murphy <dmurphy@ti.com>
Reviewed-by: NMugunthan V N <mugunthanvnm@ti.com>
Tested-by: NMugunthan V N <mugunthanvnm@ti.com>
Acked-by: NJoe Hershberger <joe.hershberger@ni.com>

Add the ability to pass the phy-handle node offset
to the phy driver.  This allows the phy driver
to access the DT subnode's data and parse accordingly.
Signed-off-by: NDan Murphy <dmurphy@ti.com>
Tested-by: NMichal Simek <michal.simek@xilinx.com>
Acked-by: NJoe Hershberger <joe.hershberger@ni.com>

Add the ability to read the phy-handle node of the
cpsw slave.  Upon reading this handle the phy-id
can be stored based on the reg node in the DT.

The phy-handle also needs to be stored and passed
to the phy to access any phy data that is available.
Signed-off-by: NDan Murphy <dmurphy@ti.com>
Tested-by: NMugunthan V N <mugunthanvnm@ti.com>
Acked-by: NJoe Hershberger <joe.hershberger@ni.com>

Enable eth driver model for dra74_evm as cpsw supports
driver model.
Signed-off-by: NMugunthan V N <mugunthanvnm@ti.com>
Reviewed-by: NTom Rini <trini@konsulko.com>
Acked-by: NJoe Hershberger <joe.hershberger@ni.com>

Enable eth driver model for am437x_sk_evm as cpsw supports
driver model.
Signed-off-by: NMugunthan V N <mugunthanvnm@ti.com>
Reviewed-by: NTom Rini <trini@konsulko.com>
Acked-by: NJoe Hershberger <joe.hershberger@ni.com>

Enable eth driver model for am437x_gp_evm as cpsw supports
driver model.
Signed-off-by: NMugunthan V N <mugunthanvnm@ti.com>
Reviewed-by: NTom Rini <trini@konsulko.com>
Acked-by: NJoe Hershberger <joe.hershberger@ni.com>

Fix typo error for cpsw device name with proper device address
Signed-off-by: NMugunthan V N <mugunthanvnm@ti.com>
Reviewed-by: NTom Rini <trini@konsulko.com>
Acked-by: NJoe Hershberger <joe.hershberger@ni.com>

Add syscon node to cpsw device node to read mac address
from efuse.
Signed-off-by: NMugunthan V N <mugunthanvnm@ti.com>
Reviewed-by: NTom Rini <trini@konsulko.com>
Acked-by: NJoe Hershberger <joe.hershberger@ni.com>

Add syscon node to cpsw device node to read mac address
from efuse.
Signed-off-by: NMugunthan V N <mugunthanvnm@ti.com>
Reviewed-by: NTom Rini <trini@konsulko.com>
Acked-by: NJoe Hershberger <joe.hershberger@ni.com>

Different TI platforms has to read with different combination to
get the mac address from efuse. So add support to read mac address
based on machine/device compatibles.

The code is taken from Linux drivers/net/ethernet/ti/cpsw-common.c
done by Tony Lindgren.
Signed-off-by: NMugunthan V N <mugunthanvnm@ti.com>
Reviewed-by: NTom Rini <trini@konsulko.com>
Acked-by: NJoe Hershberger <joe.hershberger@ni.com>

Since dra7x platforms address bus is define as 64 bits to support
LAPE, fdtdec_get_addr() returns a invalid address for mdio based
and gmii_sel register address. Fixing this by using
fdtdec_get_addr_size_auto_noparent() which will derive address
cell and size cell from its parent.
Signed-off-by: NMugunthan V N <mugunthanvnm@ti.com>
Reviewed-by: NTom Rini <trini@konsulko.com>
Acked-by: NJoe Hershberger <joe.hershberger@ni.com>

Add platforms specific phy mode configuration bits to be used
to configure phy mode in control module.
Signed-off-by: NMugunthan V N <mugunthanvnm@ti.com>
Reviewed-by: NTom Rini <trini@konsulko.com>
Acked-by: NJoe Hershberger <joe.hershberger@ni.com>

On some boards number of slaves can be 1 when only one port
ethernet is pinned out. So do not break when slave_index and
num slaves check fails, instead continue to parse the next
child.
Signed-off-by: NMugunthan V N <mugunthanvnm@ti.com>
Reviewed-by: NTom Rini <trini@konsulko.com>
Acked-by: NJoe Hershberger <joe.hershberger@ni.com>

Since omap's spl doesn't support DM currently, do not define
DM_ETH for spl build.
Signed-off-by: NMugunthan V N <mugunthanvnm@ti.com>
Reviewed-by: NSimon Glass <sjg@chromium.org>
Reviewed-by: NTom Rini <trini@konsulko.com>
Acked-by: NJoe Hershberger <joe.hershberger@ni.com>

Provide an api to check whether the given device or machine is
compatible with the given compat string which helps in making
decisions in drivers based on device or machine compatible.

Idea taken from Linux.
Signed-off-by: NMugunthan V N <mugunthanvnm@ti.com>
Reviewed-by: NJoe Hershberger <joe.hershberger@ni.com>

The previous mv88e61xx driver was a driver for configuring the
switch, but did not integrate with the PHY/networking system, so
it could not be used as a PHY by U-boot.  This is a complete
rework to support this device as a PHY.
Signed-off-by: NKevin Smith <kevin.smith@elecsyscorp.com>
Acked-by: NPrafulla Wadaskar <prafulla@marvell.com>
Cc: Albert ARIBAUD <albert.u.boot@aribaud.net>
Cc: Joe Hershberger <joe.hershberger@ni.com>
Cc: Stefan Roese <sr@denx.de>
Cc: Marek Vasut <marex@denx.de>
Acked-by: NJoe Hershberger <joe.hershberger@ni.com>

No boards are using this driver.  Remove in preparation for a new
driver with integrated PHY support.
Signed-off-by: NKevin Smith <kevin.smith@elecsyscorp.com>
Acked-by: NJoe Hershberger <joe.hershberger@ni.com>
Cc: Prafulla Wadaskar <prafulla@marvell.com>
Cc: Albert ARIBAUD <albert.u.boot@aribaud.net>
Cc: Stefan Roese <sr@denx.de>
Cc: Marek Vasut <marex@denx.de>

Extending Kconfig for adding new platform is a lot of work
for nothing. Setting SYS_CONFIG_NAME directly in Kconfig and
remove all dependencies on TARGET_ZYNQ_* options including SPL.
As a side-effect it also remove custom init folder for ps7_init_gpl.*
files. Folder is chosen based on device-tree file.
Signed-off-by: NMichal Simek <michal.simek@xilinx.com>

The patch
"net: phy: do not read configuration register on reset"
(sha1: a058052c)
was causing regression on zynq zc702 board where Marwell 88e1118
phy was resetted after negotiation was setup.
Phy reset is done pretty early in phy_connect_dev() and doens't need to
be called again in phy code.
Signed-off-by: NMichal Simek <michal.simek@xilinx.com>

Fix zynq_gem driver to handle error from phy_config correctly.
Signed-off-by: NMichal Simek <michal.simek@xilinx.com>

Add function boot_get_fpga() which find and load bitstream to
programmable logic if fpga entry is present.
Function is supported on Xilinx devices for full and partial bitstreams
in BIN and BIT format.
Signed-off-by: NMichal Simek <michal.simek@xilinx.com>
Remove additional blankline in image.h

Propagate error code from genphy_update_link() to phy startup().
Signed-off-by: NMichal Simek <michal.simek@xilinx.com>
Acked-by: NStephen Warren <swarren@nvidia.com>

Return -ETIMEDOUT if timeout happens.
Signed-off-by: NMichal Simek <michal.simek@xilinx.com>
Acked-by: NStephen Warren <swarren@nvidia.com>

Handle error returned by phy_startup() properly.
Signed-off-by: NMichal Simek <michal.simek@xilinx.com>
Acked-by: NStephen Warren <swarren@nvidia.com>

Add FIT_FPGA_PROP that user can identify an optional
entry for fpga.
Signed-off-by: NMichal Simek <michal.simek@xilinx.com>
Reviewed-by: NSimon Glass <sjg@chromium.org>

Trivial patch.
Signed-off-by: NMichal Simek <michal.simek@xilinx.com>

ZynqMP is using fixed clocks now that's why enabling it to be available
for drivers.
Signed-off-by: NMichal Simek <michal.simek@xilinx.com>