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  1. 16 7月, 2016 1 次提交
  3. 18 5月, 2016 1 次提交
  5. 15 12月, 2015 1 次提交
    • Y
      armv8: fsl-layerscape: Make DDR non secure in MMU tables · c107c0c0
      由 York Sun 提交于 
      DDR has been set as secure in MMU tables. Non-secure master such
as SDHC DMA cannot access data correctly. Mixing secure and non-
secure MMU entries requirs the MMU tables themselves in secure
memory. This patch moves MMU tables into a secure DDR area.

Early MMU tables are changed to set DDR as non-secure. A new
table is added into final MMU tables so secure memory can have
2MB granuality.

gd->secure_ram tracks the location of this secure memory. For
ARMv8 SoCs, the RAM base is not zero and RAM is divided into several
banks. gd->secure_ram needs to be maintained before using. This
maintenance is board-specific, depending on the SoC and memory
bank of the secure memory falls into.
Signed-off-by: NYork Sun <yorksun@freescale.com>
      c107c0c0
  7. 14 12月, 2015 1 次提交
  9. 30 10月, 2015 1 次提交
  11. 24 1月, 2015 1 次提交
  13. 12 12月, 2014 1 次提交
  15. 26 9月, 2014 1 次提交
    • Y
      board/ls1021aqds: Add DDR4 support · c7eae7fc
      由 York Sun 提交于 
      LS1021AQDS has a variant with DDR4 slot. This patch adds a new defconfig
for this variant to enable DDR4 support. RAW timing parameters are not
added for DDR4. The board timing parameters are only tuned for single-
rank 1600 and 1800MT/s with Micron DIMM 9ASF51272AZ-2G1A1 due to DIMM
availability.
Signed-off-by: NYork Sun <yorksun@freescale.com>
CC: Alison Wang <alison.wang@freescale.com>
      c7eae7fc
  17. 09 9月, 2014 1 次提交
  19. 05 7月, 2014 1 次提交
  21. 13 5月, 2014 1 次提交
    • C
      powerpc/85xx: Add T4240RDB board support · 0b2e13d9
      由 Chunhe Lan 提交于 
      T4240RDB board Specification
----------------------------
Memory subsystem:
   6GB DDR3
   128MB NOR flash
   2GB NAND flash

Ethernet:
   Eight 1G SGMII ports
   Four 10Gbps SFP+ ports

PCIe:
   Two PCIe slots

USB:
   Two USB2.0 Type A ports

SDHC:
   One SD-card port

SATA:
   One SATA port

UART:
   Dual RJ45 ports
Signed-off-by: NChunhe Lan <Chunhe.Lan@freescale.com>
[York Sun: fix CONFIG_SYS_QE_FMAN_FW_ADDR in T4240RDB.h]
      0b2e13d9
  23. 23 4月, 2014 1 次提交
  25. 26 11月, 2013 1 次提交
  27. 17 10月, 2013 2 次提交
    • P
      powerpc/t1040qds: Add T1040QDS board · 7d436078
      由 Prabhakar Kushwaha 提交于 
      T1040QDS is a high-performance computing evaluation, development and
test platform supporting the T1040 QorIQ Power Architecture™ processor.

 T1040QDS board Overview
 -----------------------
 - Four e5500 cores, each with a private 256 KB L2 cache
 - 256 KB shared L3 CoreNet platform cache (CPC)
 - Interconnect CoreNet platform
 - 32-/64-bit DDR3L/DDR4 SDRAM memory controller with ECC and interleaving
   support
 - Data Path Acceleration Architecture (DPAA) incorporating acceleration
 for the following functions:
    -  Packet parsing, classification, and distribution
    -  Queue management for scheduling, packet sequencing, and congestion
    	management
    -  Cryptography Acceleration
    - RegEx Pattern Matching Acceleration
    - IEEE Std 1588 support
    - Hardware buffer management for buffer allocation and deallocation
 - Ethernet interfaces
    - Integrated 8-port Gigabit Ethernet switch
    - Four 1 Gbps Ethernet controllers
 - SERDES Connections, 8 lanes supporting:
      — PCI Express: supporting Gen 1 and Gen 2;
      — SGMII
      — QSGMII
      — SATA 2.0
      — Aurora debug with dedicated connectors
 - DDR Controller 32-/64-bit DDR3L/DDR4 SDRAM memory controller with ECC and
   Interleaving
 -IFC/Local Bus
     - NAND flash: 8-bit, async, up to 2GB.
     - NOR: 8-bit or 16-bit, non-multiplexed, up to 512MB
     - GASIC: Simple (minimal) target within Qixis FPGA
     - PromJET rapid memory download support
 - Ethernet
     - Two on-board RGMII 10/100/1G ethernet ports.
     - PHY #0 remains powered up during deep-sleep
 - QIXIS System Logic FPGA
 - Clocks
     - System and DDR clock (SYSCLK, “DDRCLK”)
     - SERDES clocks
 - Power Supplies
 - Video
     - DIU supports video at up to 1280x1024x32bpp
 - USB
     - Supports two USB 2.0 ports with integrated PHYs
     — Two type A ports with 5V@1.5A per port.
     — Second port can be converted to OTG mini-AB
 - SDHC
     - SDHC port connects directly to an adapter card slot, featuring:
     - Supporting SD slots for: SD, SDHC (1x, 4x, 8x) and/or MMC
     — Supporting eMMC memory devices
 - SPI
    -  On-board support of 3 different devices and sizes
 - Other IO
    - Two Serial ports
    - ProfiBus port
    - Four I2C ports
Signed-off-by: NPoonam Aggrwal <poonam.aggrwal@freescale.com>
Signed-off-by: NPriyanka Jain <Priyanka.Jain@freescale.com>
Signed-off-by: NPrabhakar Kushwaha <prabhakar@freescale.com>
[York Sun: fix conflict in boards.cfg]
Acked-by-by: NYork Sun <yorksun@freescale.com>
      7d436078
    • P
      powerpc: Fix CamelCase warnings in DDR related code · 0dd38a35
      由 Priyanka Jain 提交于 
      Some DDR related structures present in fsl_ddr_dimm_params.h, fsl_ddr_sdram.h, ddr_spd.h
has various parameters with embedded acronyms capitalized that trigger the CamelCase
warning in checkpatch.pl

Convert those variable names to smallcase naming convention and modify all files
which are using these structures with modified structures.
Signed-off-by: NPriyanka Jain <Priyanka.Jain@freescale.com>
      0dd38a35
  29. 10 8月, 2013 1 次提交
    • Y
      powerpc/T4240EMU: Add T4240EMU target · 1cb19fbb
      由 York Sun 提交于 
      Add emulator support for T4240. Emulator has limited peripherals and
interfaces. Difference between emulator and T4240QDS includes:
	ECC for DDR is disabled due the procedure to load images
	No board FPGA (QIXIS)
	NOR flash has 32-bit port for higher loading speed
	IFC and I2C timing don't really matter, so set them fast
	No ethernet
Signed-off-by: NYork Sun <yorksun@freescale.com>
      1cb19fbb
  31. 15 5月, 2013 1 次提交
  33. 23 10月, 2012 1 次提交