- 16 7月, 2016 1 次提交
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由 York Sun 提交于
Secure_ram variable was put in generic global data. But only ARMv8 uses this variable. Move it to ARM specific data structure. Signed-off-by: NYork Sun <york.sun@nxp.com>
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- 18 5月, 2016 1 次提交
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由 Shengzhou Liu 提交于
Barrier transactions from CCI400 need to be disabled till the DDR is configured, otherwise it may lead to system hang. The patch adds workaround to fix the erratum. Signed-off-by: NShengzhou Liu <Shengzhou.Liu@nxp.com> Reviewed-by: NYork Sun <york.sun@nxp.com>
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- 15 12月, 2015 1 次提交
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由 York Sun 提交于
DDR has been set as secure in MMU tables. Non-secure master such as SDHC DMA cannot access data correctly. Mixing secure and non- secure MMU entries requirs the MMU tables themselves in secure memory. This patch moves MMU tables into a secure DDR area. Early MMU tables are changed to set DDR as non-secure. A new table is added into final MMU tables so secure memory can have 2MB granuality. gd->secure_ram tracks the location of this secure memory. For ARMv8 SoCs, the RAM base is not zero and RAM is divided into several banks. gd->secure_ram needs to be maintained before using. This maintenance is board-specific, depending on the SoC and memory bank of the secure memory falls into. Signed-off-by: NYork Sun <yorksun@freescale.com>
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- 14 12月, 2015 1 次提交
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由 Shaohui Xie 提交于
This patch also expose the complete DDR region(s) to Linux. Signed-off-by: NShaohui Xie <Shaohui.Xie@freescale.com> Signed-off-by: NMingkai Hu <Mingkai.Hu@freescale.com> Reviewed-by: NYork Sun <yorksun@freescale.com>
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- 30 10月, 2015 1 次提交
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由 Mingkai Hu 提交于
LS1043ARDB Specification: ------------------------- Memory subsystem: * 2GByte DDR4 SDRAM (32bit bus) * 128 Mbyte NOR flash single-chip memory * 512 Mbyte NAND flash * 16 Mbyte high-speed SPI flash * SD connector to interface with the SD memory card Ethernet: * XFI 10G port * QSGMII with 4x 1G ports * Two RGMII ports PCIe: * PCIe2 (Lanes C) to mini-PCIe slot * PCIe3 (Lanes D) to PCIe slot USB 3.0: two super speed USB 3.0 type A ports UART: supports two UARTs up to 115200 bps for console Signed-off-by: NHou Zhiqiang <B48286@freescale.com> Signed-off-by: NLi Yang <leoli@freescale.com> Signed-off-by: NMingkai Hu <Mingkai.Hu@freescale.com> Signed-off-by: NYork Sun <yorksun@freescale.com> Signed-off-by: NGong Qianyu <Qianyu.Gong@freescale.com>
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- 24 1月, 2015 1 次提交
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由 tang yuantian 提交于
Add deep sleep support on Freescale LS1021QDS platform. Signed-off-by: NTang Yuantian <Yuantian.Tang@freescale.com> [York Sun: Fix conflict in fdt.c] Reviewed-by: NYork Sun <yorksun@freescale.com>
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- 12 12月, 2014 1 次提交
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由 Alison Wang 提交于
This patch adds SD boot support for LS1021AQDS board. SPL framework is used. PBL initialize the internal RAM and copy SPL to it, then SPL initialize DDR using SPD and copy u-boot from SD card to DDR, finally SPL transfer control to u-boot. Signed-off-by: NAlison Wang <alison.wang@freescale.com> Signed-off-by: NJason Jin <jason.jin@freescale.com> Reviewed-by: NYork Sun <yorksun@freescale.com>
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- 26 9月, 2014 1 次提交
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由 York Sun 提交于
LS1021AQDS has a variant with DDR4 slot. This patch adds a new defconfig for this variant to enable DDR4 support. RAW timing parameters are not added for DDR4. The board timing parameters are only tuned for single- rank 1600 and 1800MT/s with Micron DIMM 9ASF51272AZ-2G1A1 due to DIMM availability. Signed-off-by: NYork Sun <yorksun@freescale.com> CC: Alison Wang <alison.wang@freescale.com>
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- 09 9月, 2014 1 次提交
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由 Wang Huan 提交于
LS102xA is an ARMv7 implementation. This patch is to add basic support for LS1021AQDS board. One DDR controller DUART1 is used as the console For the detail board information, please refer to README. Signed-off-by: NAlison Wang <alison.wang@freescale.com> Signed-off-by: NJason Jin <jason.jin@freescale.com> Signed-off-by: NYork Sun <yorksun@freescale.com> Signed-off-by: NYuan Yao <yao.yuan@freescale.com> Signed-off-by: NPrabhakar Kushwaha <prabhakar@freescale.com>
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- 05 7月, 2014 1 次提交
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由 York Sun 提交于
LS2085A is an ARMv8 implementation. This adds board support for emulator and simulator: Two DDR controllers UART2 is used as the console IFC timing is tightened for speedy booting Support DDR3 and DDR4 as separated targets Management Complex (MC) is enabled Support for GIC 500 (based on GICv3 arch) Signed-off-by: NYork Sun <yorksun@freescale.com> Signed-off-by: NArnab Basu <arnab.basu@freescale.com> Signed-off-by: NJ. German Rivera <German.Rivera@freescale.com> Signed-off-by: NBhupesh Sharma <bhupesh.sharma@freescale.com>
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- 13 5月, 2014 1 次提交
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由 Chunhe Lan 提交于
T4240RDB board Specification ---------------------------- Memory subsystem: 6GB DDR3 128MB NOR flash 2GB NAND flash Ethernet: Eight 1G SGMII ports Four 10Gbps SFP+ ports PCIe: Two PCIe slots USB: Two USB2.0 Type A ports SDHC: One SD-card port SATA: One SATA port UART: Dual RJ45 ports Signed-off-by: NChunhe Lan <Chunhe.Lan@freescale.com> [York Sun: fix CONFIG_SYS_QE_FMAN_FW_ADDR in T4240RDB.h]
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- 23 4月, 2014 1 次提交
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由 York Sun 提交于
T1040QDS_D4 is a variant of T1040QDS, with additional circuit to support DDR4 memory. Tested with MTA9ASF51272AZ-2G1AYESZG. Signed-off-by: NYork Sun <yorksun@freescale.com>
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- 26 11月, 2013 1 次提交
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由 York Sun 提交于
Freescale DDR driver has been used for mpc83xx, mpc85xx, mpc86xx SoCs. The similar DDR controllers will be used for ARM-based SoCs. Signed-off-by: NYork Sun <yorksun@freescale.com>
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- 17 10月, 2013 2 次提交
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由 Prabhakar Kushwaha 提交于
T1040QDS is a high-performance computing evaluation, development and test platform supporting the T1040 QorIQ Power Architecture™ processor. T1040QDS board Overview ----------------------- - Four e5500 cores, each with a private 256 KB L2 cache - 256 KB shared L3 CoreNet platform cache (CPC) - Interconnect CoreNet platform - 32-/64-bit DDR3L/DDR4 SDRAM memory controller with ECC and interleaving support - Data Path Acceleration Architecture (DPAA) incorporating acceleration for the following functions: - Packet parsing, classification, and distribution - Queue management for scheduling, packet sequencing, and congestion management - Cryptography Acceleration - RegEx Pattern Matching Acceleration - IEEE Std 1588 support - Hardware buffer management for buffer allocation and deallocation - Ethernet interfaces - Integrated 8-port Gigabit Ethernet switch - Four 1 Gbps Ethernet controllers - SERDES Connections, 8 lanes supporting: — PCI Express: supporting Gen 1 and Gen 2; — SGMII — QSGMII — SATA 2.0 — Aurora debug with dedicated connectors - DDR Controller 32-/64-bit DDR3L/DDR4 SDRAM memory controller with ECC and Interleaving -IFC/Local Bus - NAND flash: 8-bit, async, up to 2GB. - NOR: 8-bit or 16-bit, non-multiplexed, up to 512MB - GASIC: Simple (minimal) target within Qixis FPGA - PromJET rapid memory download support - Ethernet - Two on-board RGMII 10/100/1G ethernet ports. - PHY #0 remains powered up during deep-sleep - QIXIS System Logic FPGA - Clocks - System and DDR clock (SYSCLK, “DDRCLK”) - SERDES clocks - Power Supplies - Video - DIU supports video at up to 1280x1024x32bpp - USB - Supports two USB 2.0 ports with integrated PHYs — Two type A ports with 5V@1.5A per port. — Second port can be converted to OTG mini-AB - SDHC - SDHC port connects directly to an adapter card slot, featuring: - Supporting SD slots for: SD, SDHC (1x, 4x, 8x) and/or MMC — Supporting eMMC memory devices - SPI - On-board support of 3 different devices and sizes - Other IO - Two Serial ports - ProfiBus port - Four I2C ports Signed-off-by: NPoonam Aggrwal <poonam.aggrwal@freescale.com> Signed-off-by: NPriyanka Jain <Priyanka.Jain@freescale.com> Signed-off-by: NPrabhakar Kushwaha <prabhakar@freescale.com> [York Sun: fix conflict in boards.cfg] Acked-by-by: NYork Sun <yorksun@freescale.com>
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由 Priyanka Jain 提交于
Some DDR related structures present in fsl_ddr_dimm_params.h, fsl_ddr_sdram.h, ddr_spd.h has various parameters with embedded acronyms capitalized that trigger the CamelCase warning in checkpatch.pl Convert those variable names to smallcase naming convention and modify all files which are using these structures with modified structures. Signed-off-by: NPriyanka Jain <Priyanka.Jain@freescale.com>
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- 10 8月, 2013 1 次提交
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由 York Sun 提交于
Add emulator support for T4240. Emulator has limited peripherals and interfaces. Difference between emulator and T4240QDS includes: ECC for DDR is disabled due the procedure to load images No board FPGA (QIXIS) NOR flash has 32-bit port for higher loading speed IFC and I2C timing don't really matter, so set them fast No ethernet Signed-off-by: NYork Sun <yorksun@freescale.com>
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- 15 5月, 2013 1 次提交
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由 York Sun 提交于
Update the timing table to support more rank density, based on the theory that similar density DIMMs have similar clock adjust and write level start timing. Update the timing for 1600 and 1866 MT/s. Tested with Micron MT18JSF1G72AZ-1G9E1 DIMMs, iDIMM M3CN-4GMJ3C0C-M92. Signed-off-by: NYork Sun <yorksun@freescale.com> Signed-off-by: NAndy Fleming <afleming@freescale.com>
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- 23 10月, 2012 1 次提交
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由 York Sun 提交于
The T4240QDS is a high-performance computing evaluation, development and test platform supporting the T4240 QorIQ Power Architecture™ processor. SERDES Connections 32 lanes grouped into four 8-lane banks Two “front side” banks dedicated to Ethernet Two “back side” banks dedicated to other protocols DDR Controllers Three independant 64-bit DDR3 controllers Supports rates up to 2133 MHz data-rate Supports two DDR3/DDR3LP UDIMM/RDIMMs per controller QIXIS System Logic FPGA Each DDR controller has two DIMM slots. The first slot of each controller has up to 4 chip selects to support single-, dual- and quad-rank DIMMs. The second slot has only 2 chip selects to support single- and dual-rank DIMMs. At any given time, up to total 4 chip selects can be used. Detail information can be found in doc/README.t4qds Signed-off-by: NYork Sun <yorksun@freescale.com> Signed-off-by: NAndy Fleming <afleming@freescale.com> Signed-off-by: NKumar Gala <galak@kernel.crashing.org> Signed-off-by: NPrabhakar Kushwaha <prabhakar@freescale.com> Signed-off-by: NShengzhou Liu <Shengzhou.Liu@freescale.com> Signed-off-by: NRoy Zang <tie-fei.zang@freescale.com> Signed-off-by: NAndy Fleming <afleming@freescale.com>
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