In preparation for creating an Fdt base class, rename this file to indicate
it is the normal Fdt implementation.
Signed-off-by: NSimon Glass <sjg@chromium.org>

Rather than have dtc worry about which fdt library to use, move this into
a helper file. Add a function which creates a new Fdt object and scans it,
regardless of the implementation.
Signed-off-by: NSimon Glass <sjg@chromium.org>

This should be in with the other system includes. Move it.
Signed-off-by: NSimon Glass <sjg@chromium.org>

It is more useful to have this method raise an error when something goes
wrong. Make this the default and adjust the few callers that don't want to
use it this way.
Signed-off-by: NSimon Glass <sjg@chromium.org>

This complements the size/fatsize/ext4size commands added in
commit cf659819
load, save and ls are already implemented for hostfs, now tests can
cover the same operations on hostfs and emulated block devices.
Signed-off-by: NStefan Brüns <stefan.bruens@rwth-aachen.de>
Acked-by: NSimon Glass <sjg@chromium.org>

Signed-off-by: NStefan Brüns <stefan.bruens@rwth-aachen.de>
Acked-by: NSimon Glass <sjg@chromium.org>
Changed 'Sandbox' to 'sandbox' in subject:
Signed-off-by: NSimon Glass <sjg@chromium.org>

Import the latest version from the Diag software.

  - Support LD21 SoC (including DDR chips in the package)
  - Per-board granule adjustment for both reference and TV boards
  - Misc cleanups
Signed-off-by: NMasahiro Yamada <yamada.masahiro@socionext.com>

Initialize the DPLL (PLL for DRAM) in SPL, and others in U-Boot
proper.  Split the common code into pll-base-ld20.c for easier
re-use.
Signed-off-by: NMasahiro Yamada <yamada.masahiro@socionext.com>

Now PLLs for DRAM controller are initialized in SPL, and the others
in U-Boot proper.  Setting up all of them in a single directory will
be helpful when we want to share code between SPL and U-Boot proper.
Signed-off-by: NMasahiro Yamada <yamada.masahiro@socionext.com>

The PLL for the DRAM interface must be initialized in SPL, but the
others can be delayed until U-Boot proper.  Move them from SPL to
U-Boot proper to save the precious SPL memory footprint.
Signed-off-by: NMasahiro Yamada <yamada.masahiro@socionext.com>

Basically, this should not be configured by users.
Signed-off-by: NMasahiro Yamada <yamada.masahiro@socionext.com>

This is the last code in the mach-uniphier/pinctrl/ directory.
Push the remaining code out to delete the directory entirely.
Signed-off-by: NMasahiro Yamada <yamada.masahiro@socionext.com>

Use the pin-mux data in the pinctrl drivers by directly calling
pinctrl_generic_set_state().
Signed-off-by: NMasahiro Yamada <yamada.masahiro@socionext.com>

This will be needed for setting up the System Bus pin-mux via the
LD11/LD20 pinctrl driver.
Signed-off-by: NMasahiro Yamada <yamada.masahiro@socionext.com>

The NAND subsystem has not supported the Driver Model yet, but the
NAND pin-mux data are already in the pinctrl drivers.  Use them by
calling pinctrl_generic_set_state() directly.
Signed-off-by: NMasahiro Yamada <yamada.masahiro@socionext.com>

These settings are nicely cared by the pinctrl driver now.  Remove.
Signed-off-by: NMasahiro Yamada <yamada.masahiro@socionext.com>

This is enabled by default for all the supported boot modes.
Signed-off-by: NMasahiro Yamada <yamada.masahiro@socionext.com>

Now all UniPhier SoCs support a pinctrl driver.  Select (SPL_)PINCTRL
since it is mandatory even for base use.
Signed-off-by: NMasahiro Yamada <yamada.masahiro@socionext.com>

DT-side updates to make pinctrl on sLD3 SoC really available.
Signed-off-by: NMasahiro Yamada <yamada.masahiro@socionext.com>

Add pin-mux support for UniPhier sLD3 SoC.
Signed-off-by: NMasahiro Yamada <yamada.masahiro@socionext.com>

On LD4 SoC or later, the pin-mux registers are 8bit wide, while 4bit
wide on sLD3 SoC.  Support it for the sLD3 pinctrl driver.
Signed-off-by: NMasahiro Yamada <yamada.masahiro@socionext.com>

Sinlinx SinA33 has a USB OTG port, but VBUS is controlled manually from
a jumper pad.

Enable OTG in gadget mode, as well as the download gadget and related
functions.
Signed-off-by: NChen-Yu Tsai <wens@csie.org>
Reviewed-by: NHans de Goede <hdegoede@redhat.com>
Signed-off-by: NHans de Goede <hdegoede@redhat.com>

Sinlinx SinA33 has 1 USB host port. Enable EHCI_HCD support for it.
Also enable USB mass storage support so we can access USB sticks.
Signed-off-by: NChen-Yu Tsai <wens@csie.org>
Reviewed-by: NHans de Goede <hdegoede@redhat.com>
Signed-off-by: NHans de Goede <hdegoede@redhat.com>

Sinlinx SinA33 uses PB4 for mmc0 card detect.
Signed-off-by: NChen-Yu Tsai <wens@csie.org>
Reviewed-by: NHans de Goede <hdegoede@redhat.com>
Signed-off-by: NHans de Goede <hdegoede@redhat.com>

The NanoPi NEO is a simple h3 board with 512MB RAM, ethernet, one usb
and one usb OTG connector.
Signed-off-by: NJelle van der Waa <jelle@vdwaa.nl>
Reviewed-by: NHans de Goede <hdegoede@redhat.com>
Signed-off-by: NHans de Goede <hdegoede@redhat.com>

With sunxi-musb musb_lowlevel_init() can fail when a charger; or no cable
is plugged into the otg port.

To avoid leaking the struct musb allocated by musb_init_controller()
on repeated musb_usb_probe() calls, we were caching its result.
But musb_init_controller() does more, such as calling sunxi_musb_init()
which enables the clocks.

Not calling sunxi_musb_init() causes the musb controller to stop working
after a "usb reset" since that calls musb_usb_remove() which disables the
clocks.

This commit fixes this by removing the caching of the struct returned
from musb_init_controller(), it replaces this by free-ing the allocated
memory in musb_usb_remove() and calling musb_usb_remove() on
musb_usb_probe() errors to ensure proper cleanup.

While at it also make musb_usb_probe() and musb_usb_remove() static.
Signed-off-by: NHans de Goede <hdegoede@redhat.com>

The Linux kernel musb driver expects VBUS to be off while initializing
musb. Having it on results in a repeating string of warnings, followed
by an unusable peripheral. The peripheral is only usable after
physically removing the OTG adapter, letting musb reset its state.

This partially reverts commit c9f8947e ("sunxi: usb-phy: Never
power off the usb ports")
Signed-off-by: NChen-Yu Tsai <wens@csie.org>
Reviewed-by: NHans de Goede <hdegoede@redhat.com>
Signed-off-by: NHans de Goede <hdegoede@redhat.com>

When cold-booting the ldoio0/1 regulators are always off / the
gpios are always at tristate. But when re-booting from android these
are sometimes on. Disable them at axp_init time (iow as early as possible)
to remove this difference between a cold boot and a reboot.
Signed-off-by: NHans de Goede <hdegoede@redhat.com>
Acked-by: NIan Campbell <ijc@hellion.org.uk>

New CONFIG options should be added via Kconfig. To help prevent new ad-hoc
CONFIGs from being added, give a build error when these are detected.
Signed-off-by: NSimon Glass <sjg@chromium.org>
Acked-by: NStephen Warren <swarren@nvidia.com>
Tested-by: NStephen Warren <swarren@nvidia.com>

Add a list of ad-hoc CONFIG options that don't use Kconfig. This can be used
to check that new ones are not being added.
Signed-off-by: NSimon Glass <sjg@chromium.org>

Convert CONFIG_SPL_YMODEM_SUPPORT to Kconfig

Move this option to Kconfig and tidy up existing uses.
Signed-off-by: NSimon Glass <sjg@chromium.org>

Move this option to Kconfig and tidy up existing uses.
Signed-off-by: NSimon Glass <sjg@chromium.org>

Move this option to Kconfig and tidy up existing uses.
Signed-off-by: NSimon Glass <sjg@chromium.org>

Move this option to Kconfig and tidy up existing uses.
Signed-off-by: NSimon Glass <sjg@chromium.org>

Move this option to Kconfig and tidy up existing uses.
Signed-off-by: NSimon Glass <sjg@chromium.org>

Move this option to Kconfig and tidy up existing uses.
Signed-off-by: NSimon Glass <sjg@chromium.org>

Move this option to Kconfig and tidy up existing uses.
Signed-off-by: NSimon Glass <sjg@chromium.org>