This fix makes sure that the ISWGRP0 and ISWGRP1 registers are
correctly inited. In case those registers are not initialized,
it is not possible to access the registers synthesised in the
FPGA through the bridges. Any such access produces data abort.
Signed-off-by: NMarek Vasut <marex@denx.de>
Cc: Dinh Nguyen <dinguyen@opensource.altera.com>

Rework the driver to probe the MMC controller from Device Tree
and make it mandatory. There is no longer support for probing
from the ancient qts-generated header files.

This patch now also removes previous temporary workaround.
Signed-off-by: NMarek Vasut <marex@denx.de>
Cc: Dinh Nguyen <dinguyen@opensource.altera.com>
Cc: Pantelis Antoniou <panto@antoniou-consulting.com>
Cc: Tom Rini <trini@konsulko.com>

Signed-off-by: NStefan Brüns <stefan.bruens@rwth-aachen.de>

The default config includes base.menu, not linux.list
Signed-off-by: NStefan Brüns <stefan.bruens@rwth-aachen.de>

It is easier to paste these into the command line if they are a single
common. Use line continuation instead of separate lines.
Signed-off-by: NSimon Glass <sjg@chromium.org>

MMC support works now, so it can be dropped from the todo
Signed-off-by: NSjoerd Simons <sjoerd.simons@collabora.co.uk>
Acked-by: NSimon Glass <sjg@chromium.org>
Signed-off-by: NSimon Glass <sjg@chromium.org>

Instead of creating a rockchip SPL SD card image with 32KB of zeros
which can be written to the start of an SD card, create the images with
only the useful data that should be written to an offset of 32KB on the
SD card.

The first 32 kilobytes aren't needed for bootup and only serve as
convenient way of accidentally obliterating your partition table.
Signed-off-by: NSjoerd Simons <sjoerd.simons@collabora.co.uk>
Acked-by: NSimon Glass <sjg@chromium.org>
Signed-off-by: NSimon Glass <sjg@chromium.org>

Booting the kernel fails on RK3288 (and probably other rockchip SoCs)
when the i-cache is disabled/flushed before d-cache.

I have not investigated whether this is due to U-Boot hanging or whether
it's very early in the linux boot, but following the approach of the
various rockchip U-Boot forks (first disable d-cache then i-cache) makes
things work.
Signed-off-by: NSjoerd Simons <sjoerd.simons@collabora.co.uk>
Reviewed-by: NSimon Glass <sjg@chromium.org>
Signed-off-by: NSimon Glass <sjg@chromium.org>

Now that MMC works in U-Boot add config distro command support to start
Linux in a standard fashion. One oddity here is that linux fails to load
when the fdt is relocated to above 512MB, so set fdt_high to make sure it's
loaded below that.
Signed-off-by: NSjoerd Simons <sjoerd.simons@collabora.co.uk>
Acked-by: NSimon Glass <sjg@chromium.org>
Signed-off-by: NSimon Glass <sjg@chromium.org>

With LED support enabled the SPL easily goes over the size limit (e.g.
with both Debians gcc 4.9 and 5.2 cross-compilers). Turn off LED support
in the SPL to reduce the size just enough for those compilers.
Signed-off-by: NSjoerd Simons <sjoerd.simons@collabora.co.uk>
Tweaked commit subject to remove _SUPPORT
Signed-off-by: NSimon Glass <sjg@chromium.org>

U-Boot can't use the sdio card so turn it of to prevent things getting
confused/struck when trying to use the card as storage.
Signed-off-by: NSjoerd Simons <sjoerd.simons@collabora.co.uk>
Acked-by: NSimon Glass <sjg@chromium.org>
Signed-off-by: NSimon Glass <sjg@chromium.org>

During mmc initialize probe all devices with the MMC Uclass if build
with CONFIG_DM_MMC
Signed-off-by: NSjoerd Simons <sjoerd.simons@collabora.co.uk>
Acked-by: NSimon Glass <sjg@chromium.org>
Signed-off-by: NSimon Glass <sjg@chromium.org>

The Radxa Rock pro board is rk3188 based and thus won't work with U-Boot
built for RK3288. Change the documentation to refer to the intended
board, the Radxa Rock 2, which is an RK3288-based design very similar to
the firefly
Signed-off-by: NSjoerd Simons <sjoerd.simons@collabora.co.uk>
Acked-by: NSimon Glass <sjg@chromium.org>
Signed-off-by: NSimon Glass <sjg@chromium.org>

Add a few notes on how to try out the Rockchip support so far.
Signed-off-by: NSimon Glass <sjg@chromium.org>

This builds and displays an SPL message, but does not function beyond that.
Signed-off-by: NSimon Glass <sjg@chromium.org>

The Firefly RK3288 is a suitable target board for initial mainline Rockchip
support. It includes a good set of peripherals, a recent SoC and it is
readily available.

This adds only some basic files required to allow the baord to display a
serial message in SPL and hang.
Signed-off-by: NSimon Glass <sjg@chromium.org>

Add a SPI driver for the Rockchip RK3288, using driver model. It should work
for other Rockchip SoCs also.
Signed-off-by: NSimon Glass <sjg@chromium.org>

Add an I2C driver for the Rockchip RK3288, using driver model. It should work
for other Rockchip SoCs also.
Signed-off-by: NSimon Glass <sjg@chromium.org>

Add code for starting up U-Boot SPL and U-Boot proper. This is generic and
makes use of devices provided by the board- or SoC-specific code.
Signed-off-by: NSimon Glass <sjg@chromium.org>

Add an MMC driver which supports RK3288, but may also support other SoCs.
It uses the Designware MMC device.
Signed-off-by: NSimon Glass <sjg@chromium.org>

Add code to set up the SDRAM in SPL, ready for loading U-Boot. This uses
device tree for configuration so should be able to support other RAM
configurations. It may be possible to generalise the code to support other
SoCs at some point.
Signed-off-by: NSimon Glass <sjg@chromium.org>

Add a driver which supports pin multiplexing setup for the most commonly
used peripherals.
Signed-off-by: NSimon Glass <sjg@chromium.org>

Add a driver that provides access to system controllers.
Signed-off-by: NSimon Glass <sjg@chromium.org>

We can reset the SoC using some CRU (clock/reset unit) registers. Add support
for this.
Signed-off-by: NSimon Glass <sjg@chromium.org>

PMU is the power management unit and GRF is the general register file. Both
are heavily used in U-Boot. Add header files with register definitions.
Signed-off-by: NSimon Glass <sjg@chromium.org>

Add a driver for setting up and modifying the various PLLs and peripheral
clocks on the RK3288.
Signed-off-by: NSimon Glass <sjg@chromium.org>

Add a full regulator driver for the ACT8846. This provides easy access to
voltage and current settings for each regulator.
Signed-off-by: NSimon Glass <sjg@chromium.org>

Add a driver for the ACT8846 PMIC. This supports several LDOs and BUCKs and
is connected to the I2C bus. This driver supports using a regulator driver
to access the regulators.
Signed-off-by: NSimon Glass <sjg@chromium.org>

Add header files for the peripherals and clocks supported on Rockchip
platforms. The particular implementation (and register set) for each is
SoC-specific, but it seems that the naming can be generic.
Signed-off-by: NSimon Glass <sjg@chromium.org>

This supports RK3288 at present. It does not implement functions or support
for pull up/down.
Signed-off-by: NSimon Glass <sjg@chromium.org>

The Rockchip boot ROM requires a particular file format for booting from SPI.
It consists of a 512-byte header encoded with RC4, some padding and then up
to 32KB of executable code in 2KB blocks, separated by 2KB empty blocks.

Add support to mkimage so that an SPL image (u-boot-spl-dtb.bin) can be
converted to this format. This allows booting from SPI flash on supported
machines.
Signed-off-by: NSimon Glass <sjg@chromium.org>

The Rockchip boot ROM requires a particular file format. It consists of
64KB of zeroes, a 512-byte header encoded with RC4, and then some executable
code.

Add support to mkimage so that an SPL image (u-boot-spl-dtb.bin) can be
converted to this format.
Signed-off-by: NSimon Glass <sjg@chromium.org>

Rockchip SoCs require certain formats for code that they execute, The
simplest format is a 4-byte header at the start of a binary file. Add
support for this so that we can create images that the boot ROM understands.
Signed-off-by: NSimon Glass <sjg@chromium.org>

Allow the image handler to store the original input file size so that it
can reference it later.
Signed-off-by: NSimon Glass <sjg@chromium.org>
Reviewed-by: NJoe Hershberger <joe.hershberger@ni.com>

At present there is an arbitrary limit of 4KB for padding. Rockchip needs
more than that, so remove this restriction.
Signed-off-by: NSimon Glass <sjg@chromium.org>
Reviewed-by: NJoe Hershberger <joe.hershberger@ni.com>

In SPL we need access to the CRU and other peripherals so we can set up
SDRAM. Mark these so that they will remain in the device tree.
Signed-off-by: NSimon Glass <sjg@chromium.org>

Bring in required device tree files from Linux. Since mainline Linux is
somewhat behind, use the files from the Chromium tree. We can re-sync once
further code is acccepted upstream.
Signed-off-by: NSimon Glass <sjg@chromium.org>

Add support for the Rockchip serial device using the ns16550 driver.
This uses driver model and device tree for both SPL and U-Boot proper.
Signed-off-by: NSimon Glass <sjg@chromium.org>

There can be only one do_reset(). When CONFIG_RESET is enabled this is
provided by the reset uclass, and ARM's version should be disabled.
Signed-off-by: NSimon Glass <sjg@chromium.org>