Many SPL linker scripts needlessly include linker lists (aka LGAs).
Remove them whenever possible; keep it only in the seven am335x_evm
variants (am335x_evm, am335x_evm_uart[1-5], am335x_evm_spiboot),
where there is actual content in output section .u_boot_list.

This commit keeps all u-boot.bin and u-boot-spl.bin in ARM targets
byte-identical.
Signed-off-by: NAlbert ARIBAUD <albert.u.boot@aribaud.net>

Output section .u_boot_list was left unmapped in
u-boot-spl.lds for omap-common, causing the location
counter to roll back to bteween .rodata and .data,
making __image_copy_end and _end symbols wrong.

Mapping output section .u_boot_list to memory .sram
fixes these symbols' mapping.

This modifies the SPL binary but has no functional
impact, as __image_copy_end and _end are never used
in SPLs and u_boot_list is empty for all 29 boards
affected (omap4_sdp4430 eco5pk igep0030 am335x_evm_uart3
omap3_beagle am3517_crane igep0032 mt_ventoux pcm051
am3517_evm omap3_evm_quick_mmc am335x_evm_uart2
am335x_evm_spiboot am335x_evm_uart1 omap3_evm igep0030_nand
omap3_overo igep0020 am335x_evm omap4_panda omap5_evm
am335x_evm_uart4 devkit8000 tricorder mcx twister
omap3_evm_quick_nand am335x_evm_uart5 igep0020_nand).
Signed-off-by: NAlbert ARIBAUD <albert.u.boot@aribaud.net>

Fix pin setting in MII mode
Signed-off-by: NJesse Gilles <jgilles@multitech.com>
Signed-off-by: NAndreas Bießmann <andreas.devel@googlemail.com>

As the CPU name is not configurable, using CPU string directly
Signed-off-by: NBo Shen <voice.shen@atmel.com>
Signed-off-by: NAndreas Bießmann <andreas.devel@googlemail.com>

Change nand flash partition table according to www.at91.com/linux4sam

more information: http://www.at91.com/linux4sam/bin/view/Linux4SAM/GettingStarted#Linux4SAM_NandFlash_demo_MemorySigned-off-by: NBo Shen <voice.shen@atmel.com>
[minor commit message changes]
Signed-off-by: NAndreas Bießmann <andreas.devel@googlemail.com>

Support to boot zImage
Signed-off-by: NNicolas Ferre <nicolas.ferre@atmel.com>
[Add bootz for at91rm9200, at91sam9263, at91sam9rl]
Signed-off-by: NBo Shen <voice.shen@atmel.com>
Signed-off-by: NAndreas Bießmann <andreas.devel@googlemail.com>

support to boot device tree Linux kernel
Signed-off-by: NNicolas Ferre <nicolas.ferre@atmel.com>
[Add libftd for at91rm9200, at91sam9263, at91sam9rl]
Signed-off-by: NBo Shen <voice.shen@atmel.com>
Signed-off-by: NAndreas Bießmann <andreas.devel@googlemail.com>

In master we had already taken a patch to fix the davinci GPIO code for
CONFIG_SOC_DM646X and in u-boot-ti we have additional patches to support
DA830 (which is CONFIG_SOC_DA8XX && !CONFIG_SOC_DA850).  Resolve these
conflicts manually and comment the #else/#endif lines for clarity.

Conflicts:
	arch/arm/include/asm/arch-davinci/gpio.h
	drivers/gpio/da8xx_gpio.c
Signed-off-by: NTom Rini <trini@ti.com>

Adding CPU detection support for the DRA752 ES1.0 soc.
Signed-off-by: NLokesh Vutla <lokeshvutla@ti.com>
Signed-off-by: NR Sricharan <r.sricharan@ti.com>
Reviewed-by: NTom Rini <trini@ti.com>

Adding the build support for dra7xx_evm.
Reusing omap5_evm.h config by moving it to omap5_common.h
Signed-off-by: NLokesh Vutla <lokeshvutla@ti.com>
Signed-off-by: NR Sricharan <r.sricharan@ti.com>

Adding new board files for DRA7XX socs.
The pad registers layout is changed completely from OMAP5
So introducing the new structure here and also adding the
minimal data.
Signed-off-by: NLokesh Vutla <lokeshvutla@ti.com>
Signed-off-by: NNishant Kamat <nskamat@ti.com>
Signed-off-by: NR Sricharan <r.sricharan@ti.com>
Reviewed-by: NTom Rini <trini@ti.com>
[trini: Adapt omap_mmc_init call for last 2 params]
Signed-off-by: NTom Rini <trini@ti.com>

DRA752 uses DDR3. Populating the corresponding structures
with DDR3 data.
Writing into MA registers if only MA is present in that soc.
Signed-off-by: NLokesh Vutla <lokeshvutla@ti.com>
Signed-off-by: NR Sricharan <r.sricharan@ti.com>
Reviewed-by: NTom Rini <trini@ti.com>

Control module register addresses are changed from OMAP5
to DRA7XX socs.
So adding the necessary changes for the same.
Signed-off-by: NLokesh Vutla <lokeshvutla@ti.com>
Signed-off-by: NR Sricharan <r.sricharan@ti.com>
Reviewed-by: NTom Rini <trini@ti.com>

A new DPLL DDR is added in DRA7XX socs. Now clocks to
EMIF CD is from DPLL DDR. So DPLL DDR should be locked
before initializing RAM.
Also adding other dpll data which are different from OMAP5 ES2.0.
SYS_CLK running at 20MHz is introduced in DRA7xx socs.
Signed-off-by: NLokesh Vutla <lokeshvutla@ti.com>
Signed-off-by: NR Sricharan <r.sricharan@ti.com>
Reviewed-by: NTom Rini <trini@ti.com>

PRCM register addresses are changed from OMAP5 ES2.0 to DRA7XX.
So adding the necessary register changes for DRA7XX socs.
Signed-off-by: NLokesh Vutla <lokeshvutla@ti.com>
Signed-off-by: NR Sricharan <r.sricharan@ti.com>

After power-up SRCOMP cells are by-passed by default in OMAP5.
Software has to enable these SRCOMP sells.
For ES2: All 5 SRCOMP cells needs to be enabled.
For ES1: Only 4 SRCOMP cells in core power domain are enabled.
	 The 1 in wkup domain is not enabled because smart i/os
	 of wkup domain work with default compensation code.
Signed-off-by: NR Sricharan <r.sricharan@ti.com>
Signed-off-by: NLokesh Vutla <lokeshvutla@ti.com>
Reviewed-by: NTom Rini <trini@ti.com>
Cc: Tom Rini <trini@ti.com>

Add pre calculated timing settings of LPDDR2 and DDR3 memories
present in OMAP5430 and OMAP5432 ES2.0 versions.

Also adding the DDR pad io settings required for
OMAP543X SOCs here.
Signed-off-by: NR Sricharan <r.sricharan@ti.com>
Signed-off-by: NLokesh Vutla <lokeshvutla@ti.com>
Reviewed-by: NTom Rini <trini@ti.com>
Cc: Tom Rini <trini@ti.com>

Change OPP settings as per the latest 0.5 version of
addendum for OMAP5430 ES2.0. omap4/hw_data.c is touched
here to add dummy dividers.

While here correcting OPP_NOM mpu, core frequency for
OMAP4430 ES2.x

Note that OMAP5430 ES1.0 support is still kept alive and
would be removed in a cleanup later.
Signed-off-by: NLokesh Vutla <lokeshvutla@ti.com>
Signed-off-by: NR Sricharan <r.sricharan@ti.com>
Cc: Tom Rini <trini@ti.com>
Cc: Nishanth Menon <nm@ti.com>

PRCM register addresses are changed from ES1.0 to ES2.0 due to
PER power domain getting moved to CORE power domain.

So adding the nessecary register changes for the same.
Signed-off-by: NR Sricharan <r.sricharan@ti.com>
Reviewed-by: NTom Rini <trini@ti.com>
Cc: Tom Rini <trini@ti.com>

Adding the CPU detection suport for OMAP5430 and
OMAP5432 ES2.0 SOCs.
Signed-off-by: NR Sricharan <r.sricharan@ti.com>
Cc: Tom Rini <trini@ti.com>
Cc: Nishanth Menon <nm@ti.com>

There is some code duplication in the ddr io settings code.
This is avoided by moving the data to a Soc specific place and
letting the code generic.

This avoids unnessecary code addition for future socs.
Signed-off-by: NLokesh Vutla <lokeshvutla@ti.com>
Reviewed-by: NTom Rini <trini@ti.com>

A seperate omap_sys_ctrl_regs structure is defined for
omap4 & 5. If there is any change in control module for
any of the ES versions, a new structure needs to be created.
In order to remove this dependency, making the register
structure generic for all the omap4+ boards.
Signed-off-by: NR Sricharan <r.sricharan@ti.com>
Signed-off-by: NLokesh Vutla <lokeshvutla@ti.com>
Reviewed-by: NTom Rini <trini@ti.com>

Removing the duplicated code in ddr3 initialization.
Also creating structure for lpddr2 mode registers to
avoid unnessecary revision checks.

These change reduces code addition for future Socs.
Signed-off-by: NR Sricharan <r.sricharan@ti.com>
Signed-off-by: NLokesh Vutla <lokeshvutla@ti.com>
Reviewed-by: NTom Rini <trini@ti.com>

The pmic code is duplicated for OMAP 4 and 5.
Instead move the data to Soc specific place and
share the code.
Signed-off-by: NR Sricharan <r.sricharan@ti.com>
Signed-off-by: NLokesh Vutla <lokeshvutla@ti.com>
Reviewed-by: NTom Rini <trini@ti.com>

Currently there is quite a lot of code which
is duplicated in the clocks code for OMAP 4 and 5
Socs. Avoiding this here by moving the clocks
data to a SOC specific place and the sharing the
common code.

This helps in addition of a new Soc with minimal
changes.
Signed-off-by: NR Sricharan <r.sricharan@ti.com>
Signed-off-by: NLokesh Vutla <lokeshvutla@ti.com>
Reviewed-by: NTom Rini <trini@ti.com>

The current PRCM structure prototype directly matches the hardware
register layout. So there is a need to change this for every new silicon
revision which has register space changes.

Avoiding this by making the prototye generic and populating the register
addresses seperately for all Socs.
Signed-off-by: NR Sricharan <r.sricharan@ti.com>
Signed-off-by: NLokesh Vutla <lokeshvutla@ti.com>

Now SDRAM initialization is done on the basis of omap revision.
Instead this should be done on basis of SDRAM type read from
EMIF_SDRAM_CONFIG register. This will be helpful to avoid
unnessecary cpu checks for new boards
Signed-off-by: NR Sricharan <r.sricharan@ti.com>
Signed-off-by: NLokesh Vutla <lokeshvutla@ti.com>
Reviewed-by: NTom Rini <trini@ti.com>

Define CONFIG_SPLASHIMAGE_GUARD to prevent splashimage from being
set to a value that will cause U-Boot to hang while displaying a
splash screen.
Signed-off-by: NNikita Kiryanov <nikita@compulab.co.il>
Acked-by: NIgor Grinberg <grinberg@compulab.co.il>

On some architectures certain values of splashimage will lead to
a data abort exception.

Document the problem, and implement a callback for splashimage to
reject such values.

Cc: Anatolij Gustschin <agust@denx.de>
Cc: Wolfgang Denk <wd@denx.de>
Signed-off-by: NNikita Kiryanov <nikita@compulab.co.il>
Acked-by: NIgor Grinberg <grinberg@compulab.co.il>

Before submitting packets to cpdma, phy status is updated on every packet
which leads to delay in packet send intern reduces the Ethernet performance.
Checking mdio status for each packet will reduce timetaken to send a packet
and there by increasing the Ethernet performance. With this the performance
is increased from 208KiB/s to 375KiB/s on EVMsk
Signed-off-by: NMugunthan V N <mugunthanvnm@ti.com>

With v3.9 and later of the Linux Kernel defaulting to multi-platform
images with omap2plus_defconfig, uImage isn't builtable anymore by
default.  Add CONFIG_CMD_BOOTZ so that we can still boot something the
kernel spits out.

Cc: Sricharan R <r.sricharan@ti.com>
Signed-off-by: NTom Rini <trini@ti.com>
Reviewed-by: NR Sricharan <r.sricharan@ti.com>

With v3.9 and later of the Linux Kernel defaulting to multi-platform
images with omap2plus_defconfig, uImage isn't builtable anymore by
default.  Add CONFIG_CMD_BOOTZ so that we can still boot something the
kernel spits out.
Signed-off-by: NTom Rini <trini@ti.com>

With v3.9 and later of the Linux Kernel defaulting to multi-platform
images with omap2plus_defconfig, uImage isn't builtable anymore by
default.  Add CONFIG_CMD_BOOTZ so that we can still boot something the
kernel spits out.

Cc: Sricharan R <r.sricharan@ti.com>
Signed-off-by: NTom Rini <trini@ti.com>
Reviewed-by: NR Sricharan <r.sricharan@ti.com>

With v3.9 and later of the Linux Kernel defaulting to multi-platform
images with omap2plus_defconfig, uImage isn't builtable anymore by
default.  Add CONFIG_CMD_BOOTZ so that we can still boot something the
kernel spits out.
Signed-off-by: NTom Rini <trini@ti.com>
Acked-by: NPeter Korsgaard <jacmet@sunsite.dk>

Expose the enable_gpmc_cs_config() function so AM33xx based boards can register GPMC chip selects.

Changes in V4:
- Fix checkpatch errors (TAB -> space mangling)

Changes in V3:
- Fix line wrapping

Changes in V2:
- Indicate this is for AM33xx (not OMAP2)
Signed-off-by: NMark Jackson <mpfj@newflow.co.uk>
Acked-by: NPeter Korsgaard <jacmet@sunsite.dk>

In order to use SPL boot from OneNAND we should initialize the gpmc.
Signed-off-by: NEnric Balletbo i Serra <eballetbo@iseebcn.com>

This patch will allow use SPL to boot an u-boot from the OneNAND.

Tested with IGEPv2 board with a OneNAND from Numonyx
Signed-off-by: NEnric Balletbo i Serra <eballetbo@iseebcn.com>
[trini: Add <spl.h> hunk to fix warning]
Signed-off-by: NTom Rini <trini@ti.com>

Tested with an IGEPv2 board seems that current onenand_spl_load_image implementation
doesn't work. This patch fixes this function changing the read loop and reading the
onenand blocks from page to page.

Tested with various IGEP based boards with a OneNAND from Numonyx.
Signed-off-by: NEnric Balletbo i Serra <eballetbo@iseebcn.com>

Some ONENAND related defines use the term ONE_NAND instead of
ONENAND, as the technology name is ONENAND this patch replaces
all these defines.
Signed-off-by: NEnric Balletbo i Serra <eballetbo@iseebcn.com>