- 10 8月, 2013 1 次提交
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由 Priyanka Jain 提交于
BSC9132QDS is a Freescale Reference Design Board for BSC9132 SoC which is a integrated device that contains two powerpc e500v2 cores and two DSP starcores. To support DSP starcore -Creating LAW and TLB for DSP-CCSR space. -Creating LAW for DSP-core subsystem M2 and M3 memory -Creating LAW for 1GB DDR which is connected exclusively to DSP-cores Signed-off-by: NManish Jaggi <manish.jaggi@freescale.com> Signed-off-by: NPriyanka Jain <Priyanka.Jain@freescale.com> Acked-by: NYork Sun <yorksun@freescale.com>
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- 24 7月, 2013 1 次提交
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由 Wolfgang Denk 提交于
Signed-off-by: NWolfgang Denk <wd@denx.de> [trini: Fixup common/cmd_io.c] Signed-off-by: NTom Rini <trini@ti.com>
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- 21 6月, 2013 2 次提交
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由 Prabhakar Kushwaha 提交于
e500v2 processor does not support 8K page size TLB entries. So create new TLB entry only during NAND SPL boot. Signed-off-by: NPrabhakar Kushwaha <prabhakar@freescale.com> Signed-off-by: NAndy Fleming <afleming@freescale.com>
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由 Prabhakar Kushwaha 提交于
- Add NAND boot target - defines constants - Add spl_minimal.c to initialise DDR - update TLB, LAW entries as per NAND boot Signed-off-by: NPrabhakar Kushwaha <prabhakar@freescale.com> Signed-off-by: NAndy Fleming <afleming@freescale.com>
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- 31 1月, 2013 1 次提交
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由 Prabhakar Kushwaha 提交于
BSC9132QDS is a Freescale reference design board for BSC9132 SoC. BSC9132 SOC is an integrated device that targets the evolving Microcell, Picocell, and Enterprise-Femto base station market subsegments. It combines Power Architecture e500v2 and DSP StarCore SC3850 core technologies with MAPLE-B2F baseband acceleration processing elements. BSC9132QDS Overview -------------------- 2Gbyte DDR3 (on board DDR), Dual Ranki 32Mbyte 16bit NOR flash 128Mbyte 2K page size NAND Flash 256 Kbit M24256 I2C EEPROM 128 Mbit SPI Flash memory SD slot USB-ULPI eTSEC1: Connected to SGMII PHY eTSEC2: Connected to SGMII PHY PCIe CPRI SerDes I2C RTC DUART interface: supports one UARTs up to 115200 bps for console display Apart from the above it also consists various peripherals to support DSP functionalities. This patch adds support for mainly Power side functionalities and peripherals Signed-off-by: NNaveen Burmi <NaveenBurmi@freescale.com> Signed-off-by: NPoonam Aggrwal <poonam.aggrwal@freescale.com> Signed-off-by: NPrabhakar Kushwaha <prabhakar@freescale.com> Signed-off-by: NAndy Fleming <afleming@freescale.com>
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- 30 9月, 2011 1 次提交
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由 Poonam Aggrwal 提交于
Boot methods supported: NOR Flash, SPI Flash and SDCARD This patch adds the following basic interfaces: DDR3, eTSEC, DUART, I2C, SD/MMC, USB, SATA, PCIe, NOR Flash, SPI Flash. P1010RDB Overview ----------------- 1Gbyte DDR3 (on board DDR) Local Bus (IFC): 32Mbyte 16bit NOR flash 32Mbyte SLC NAND Flash 64KB CPLD device(GPCM interface) SPI Flash: 128 Mbit SPI Flash memory SD/MMC: connector to interface with the SD memory card SATA: 1 internal SATA connect to 2.5. 160G SATA2 HDD 1 eSATA connector to rear panel USB 2.0: x1 USB 2.0 port: connected via a UTMI PHY to Mini-AB interface. x1 USB 2.0 port: directly connected to Mini-AB interface Ethernet eTSEC: eTSEC1: Connected to RGMII PHY VSC8641XKO eTSEC2: Connected to SGMII PHY VSC8221 eTSEC3: Connected to SGMII PHY VSC8221 eCAN: Two DB-9 female connectors for Field bus interface UART: supports two UARTs up to 115200 bps for console TDM: 2 FXS ports connected via an external SLIC to the TDM interface. SLIC: SPI SLIC I2C: Serial EEprom Real time clock 256 Kbit M24256 I2C EEPROM PCIe: PCIe and mPCIe connectors. Signed-off-by: NPoonam Aggrwal <poonam.aggrwal@freescale.com> Signed-off-by: NDipen Dudhat <dipen.dudhat@freescale.com> Signed-off-by: NPrabhakar Kushwaha <prabhakar@freescale.com> Signed-off-by: NRamneek Mehresh <ramneek.mehresh@freescale.com> Signed-off-by: NBhaskar Upadhaya <Bhaskar.Upadhaya@freescale.com> Signed-off-by: NYork Sun <yorksun@freescale.com> Signed-off-by: NKumar Gala <galak@kernel.crashing.org>
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- 04 4月, 2011 2 次提交
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由 Poonam Aggrwal 提交于
Add support for 36-bit address map for NOR, SD, and SPI boot cfgs. Signed-off-by: NPoonam Aggrwal <poonam.aggrwal@freescale.com> Signed-off-by: NPriyanka Jain <priyanka.jain@freescale.com> Signed-off-by: NKumar Gala <galak@kernel.crashing.org>
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由 Priyanka Jain 提交于
Using DDR as RAMBOOT base instead of L2SRAM for SDCard and SPI Flash boot loaders because: - P1_P2_RDB boards have soldered DDR so no need for SPD - Also P102x has 256K L2 cache size so becomes a limiting factor for size of image that could be loaded in SRAM mode and would require three stage boot loader (TPL). Changes done: 1. CONFIG_SYS_TEXT_BASE to 0x11000000 2. CONFIG_RESET_VECTOR_ADDRESS to 0x1107fffc Signed-off-by: NPriyanka Jain <Priyanka.Jain@freescale.com> Signed-off-by: NPoonam Aggrwal <Poonam.Aggrwal@freescale.com> Signed-off-by: NDipen Dudhat <Dipen.Dudhat@freescale.com> Signed-off-by: NKumar Gala <galak@kernel.crashing.org>
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- 24 3月, 2011 1 次提交
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由 Prabhakar Kushwaha 提交于
Update the PCIe address map to match standard FSL memory map. Additionally, fix the TLBs so the cover the PCIe address space properly so cards plugged in like an e1000 work correctly. Signed-off-by: NPrabhakar Kushwaha <prabhakar@freescale.com> Signed-off-by: NKumar Gala <galak@kernel.crashing.org>
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- 20 1月, 2011 1 次提交
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由 Prabhakar Kushwaha 提交于
u-boot cannot be compiled after disabling CONFIG_PCI. Place PCI related codes under #ifdef CONFIG_PCI Signed-off-by: NPrabhakar Kushwaha <prabhakar@freescale.com> Signed-off-by: NKumar Gala <galak@kernel.crashing.org>
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- 06 1月, 2010 1 次提交
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由 Kumar Gala 提交于
We already map the page cache-inhibited. There is no reason we shouldn't also be marking it guarded to prevent speculative accesses. Signed-off-by: NKumar Gala <galak@kernel.crashing.org>
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- 16 10月, 2009 1 次提交
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由 Dipen Dudhat 提交于
NAND Boot support for P1 and P2 series RDB platforms. This patch is derived from NAND Boot support on MPC8536DS. Signed-off-by: NDipen Dudhat <dipen.dudhat@freescale.com> Signed-off-by: NKumar Gala <galak@kernel.crashing.org>
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- 29 8月, 2009 1 次提交
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由 Poonam Aggrwal 提交于
The code base adds P1 & P2 RDB platforms support. The folder and file names can cater to future SOCs of P1/P2 family. P1 & P2 processors are 85xx platforms, part of Freescale QorIQ series. Tested following on P2020RDB: 1. eTSECs 2. DDR, NAND, NOR, I2C. Signed-off-by: NPoonam Aggrwal <poonam.aggrwal@freescale.com> Signed-off-by: NKumar Gala <galak@kernel.crashing.org>
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