1. 11 10月, 2019 14 次提交
  2. 10 10月, 2019 1 次提交
    • T
      Merge tag 'xilinx-for-v2020.01' of https://gitlab.denx.de/u-boot/custodians/u-boot-microblaze · 44fb0d6c
      Tom Rini 提交于
      Xilinx/FPGA changes for v2020.01
      
      FPGA:
      - Enable fpga loading on Versal
      - Minor fix
      
      Microblaze:
      - Fix LMB configurations to support initrds
      - Some other cleanups
      
      Zynq:
      - Minor config/dt changes
      - Add distro boot support for usb1 and mmc1
      - Remove Xilinx private boot commands and use only distro boot
      
      ZynqMP:
      - Kconfig cleanups, defconfig updates
      - Update some dt files
      - Add firmware driver for talking to PMUFW
      - Extend distro boot support for jtag
      - Add new IDs
      - Add system controller configurations
      - Convert code to talk firmware via mailbox or SMCs
      
      Versal:
      - Add board_late_init()
      - Add run time DT memory setup
      - Add DFU support
      - Extend distro boot support for jtag and dfu
      - Add clock driver
      - Tune mini configurations
      
      Xilinx:
      - Improve documentation (boot scripts, dt binding)
      - Enable run time initrd_high calculation
      - Define default SYS_PROMPT
      - Add zynq/zynqmp virtual defconfig
      
      Drivers:
      - Add Xilinx mailbox driver for talking to firmware
      - Clean zynq_gem for Versal
      - Move ZYNQ_HISPD_BROKEN to Kconfig
      - Wire genphy_init() in phy.c
      - Add Xilinx gii2rgmii bridge
      - Cleanup zynq_sdhci
      - dwc3 fix
      - zynq_gpio fix
      - axi_emac fix
      
      Others:
      - apalis-tk1 - clean config file
      44fb0d6c
  3. 09 10月, 2019 12 次提交
  4. 08 10月, 2019 13 次提交