add spi alias for qspi so that spi probes the device and driver
successfully.
Signed-off-by: NMugunthan V N <mugunthanvnm@ti.com>
Reviewed-by: NSimon Glass <sjg@chromium.org>
Reviewed-by: NJagan Teki <jteki@openedev.com>

Since OMAP's spl doesn't support DM currently, do not define DM_SPI and
DM_SPI_FLASH for spl build.
Signed-off-by: NMugunthan V N <mugunthanvnm@ti.com>
Reviewed-by: NJagan Teki <jteki@openedev.com>

spi bus can support dual and quad wire data transfers for tx and
rx. So defining dual and quad modes for both tx and rx. Also add
support to parse bus width used for spi tx and rx transfers.
Signed-off-by: NMugunthan V N <mugunthanvnm@ti.com>
Reviewed-by: NJagan Teki <jteki@openedev.com>
Signed-off-by: NJagan Teki <jteki@openedev.com>

Prepare driver for DM conversion.
Signed-off-by: NMugunthan V N <mugunthanvnm@ti.com>
Reviewed-by: NJagan Teki <jteki@openedev.com>

Changing the ti_qspi_priv structure and its instance names from
to priv for driver mode conversion.
Signed-off-by: NMugunthan V N <mugunthanvnm@ti.com>
Reviewed-by: NSimon Glass <sjg@chromium.org>
Reviewed-by: NTom Rini <trini@konsulko.com>
Reviewed-by: NJagan Teki <jteki@openedev.com>

To enable memory map in dra7xx, specific chip select must be
written to control module register. But this hard coded to chip
select 1, fixing it by writing the specific chip select value to
control module register.
Signed-off-by: NMugunthan V N <mugunthanvnm@ti.com>
Reviewed-by: NSimon Glass <sjg@chromium.org>
Reviewed-by: NTom Rini <trini@konsulko.com>
Reviewed-by: NJagan Teki <jteki@openedev.com>

Added SPI_TX_DUAL mode flag.

Cc: Bin Meng <bmeng.cn@gmail.com>
Cc: Mugunthan V N <mugunthanvnm@ti.com>
Tested-by: NJagan Teki <jteki@openedev.com>
Signed-off-by: NJagan Teki <jteki@openedev.com>

SLOW, FAST, DUAL, DUAL_IO, QUAD, QUAD_IO changed order to
SLOW, FAST, DUAL, QUAD, DUAL_IO, QUAD_IO

Cc: Simon Glass <sjg@chromium.org>
Cc: Michal Simek <michal.simek@xilinx.com>
Cc: Siva Durga Prasad Paladugu <sivadur@xilinx.com>
Tested-by: NJagan Teki <jteki@openedev.com>
Reviewed-by: NBin Meng <bmeng.cn@gmail.com>
Signed-off-by: NJagan Teki <jteki@openedev.com>

- Add comments on mode_rx
- Tab space's

Cc: Simon Glass <sjg@chromium.org>
Cc: Michal Simek <michal.simek@xilinx.com>
Cc: Siva Durga Prasad Paladugu <sivadur@xilinx.com>
Tested-by: NMugunthan V N <mugunthanvnm@ti.com>
Tested-by: NBin Meng <bmeng.cn@gmail.com>
Tested-by: NJagan Teki <jteki@openedev.com>
Reviewed-by: NBin Meng <bmeng.cn@gmail.com>
Signed-off-by: NJagan Teki <jteki@openedev.com>

Used BIT macro like 1 << nr as BIT(nr) where nr is 0...n

Cc: Simon Glass <sjg@chromium.org>
Cc: Michal Simek <michal.simek@xilinx.com>
Cc: Siva Durga Prasad Paladugu <sivadur@xilinx.com>
Tested-by: NMugunthan V N <mugunthanvnm@ti.com>
Tested-by: NBin Meng <bmeng.cn@gmail.com>
Tested-by: NJagan Teki <jteki@openedev.com>
Reviewed-by: NBin Meng <bmeng.cn@gmail.com>
Signed-off-by: NJagan Teki <jteki@openedev.com>

Fixed bit assignment with flags members on spi_slave{}

Cc: Simon Glass <sjg@chromium.org>
Cc: Michal Simek <michal.simek@xilinx.com>
Cc: Siva Durga Prasad Paladugu <sivadur@xilinx.com>
Tested-by: NMugunthan V N <mugunthanvnm@ti.com>
Tested-by: NBin Meng <bmeng.cn@gmail.com>
Tested-by: NJagan Teki <jteki@openedev.com>
Reviewed-by: NBin Meng <bmeng.cn@gmail.com>
Signed-off-by: NJagan Teki <jteki@openedev.com>

This patch moves flags macro's to respective member
position on spi_slave{}, for better readabilty and
finding the respective member macro's easily.

Cc: Simon Glass <sjg@chromium.org>
Cc: Bin Meng <bmeng.cn@gmail.com>
Cc: Michal Simek <michal.simek@xilinx.com>
Cc: Siva Durga Prasad Paladugu <sivadur@xilinx.com>
Tested-by: NMugunthan V N <mugunthanvnm@ti.com>
Tested-by: NJagan Teki <jteki@openedev.com>
Signed-off-by: NJagan Teki <jteki@openedev.com>

Since spi rx mode macro's are renamed to simple and
meaninfull, this patch will rename the respective
structure members.

Cc: Simon Glass <sjg@chromium.org>
Cc: Bin Meng <bmeng.cn@gmail.com>
Cc: Michal Simek <michal.simek@xilinx.com>
Cc: Siva Durga Prasad Paladugu <sivadur@xilinx.com>
Tested-by: NMugunthan V N <mugunthanvnm@ti.com>
Tested-by: NJagan Teki <jteki@openedev.com>
Signed-off-by: NJagan Teki <jteki@openedev.com>

SPI_OPM_RX_AS 	- SPI_RX_SLOW
SPI_OPM_RX_AF	- SPI_RX_FAST
SPI_OPM_RX_DOUT	- SPI_RX_DUAL
SPI_OPM_RX_QOF	- SPI_RX_QUAD

Cc: Simon Glass <sjg@chromium.org>
Cc: Michal Simek <michal.simek@xilinx.com>
Cc: Siva Durga Prasad Paladugu <sivadur@xilinx.com>
Tested-by: NMugunthan V N <mugunthanvnm@ti.com>
Tested-by: NBin Meng <bmeng.cn@gmail.com>
Tested-by: NJagan Teki <jteki@openedev.com>
Reviewed-by: NBin Meng <bmeng.cn@gmail.com>
Signed-off-by: NJagan Teki <jteki@openedev.com>

SPI_OPM_RX_DIO and SPI_OPM_RX_QIOF are rx IO
commands/opmodes for dual and quad. Usually IO
operation's are referred to flash protocol rather
with spi controller protocol, these are still present
in flash side for the usage of spi-nor controllers.

Cc: Simon Glass <sjg@chromium.org>
Cc: Michal Simek <michal.simek@xilinx.com>
Cc: Siva Durga Prasad Paladugu <sivadur@xilinx.com>
Tested-by: NMugunthan V N <mugunthanvnm@ti.com>
Tested-by: NBin Meng <bmeng.cn@gmail.com>
Tested-by: NJagan Teki <jteki@openedev.com>
Reviewed-by: NBin Meng <bmeng.cn@gmail.com>
Signed-off-by: NJagan Teki <jteki@openedev.com>

SPI_OPM_RX_EXTN is a combination of all rx opmode's
and spi driver shall use any one of the rx mode at
a time not the combination and it is true in case of
flash where spi_flash_table mention combination of
supported read opmodes so-that the required one
will pick based on the rx mode from spi driver.

Cc: Simon Glass <sjg@chromium.org>
Cc: Michal Simek <michal.simek@xilinx.com>
Cc: Siva Durga Prasad Paladugu <sivadur@xilinx.com>
Tested-by: NMugunthan V N <mugunthanvnm@ti.com>
Tested-by: NBin Meng <bmeng.cn@gmail.com>
Tested-by: NJagan Teki <jteki@openedev.com>
Reviewed-by: NBin Meng <bmeng.cn@gmail.com>
Signed-off-by: NJagan Teki <jteki@openedev.com>

While setting quad bit on spansion, macronix code
is writing only particular quad bit this may give
wrong functionality with other register bits,
So this patch fix the issue where it with write
previous read reg status along  particular quad bit.

Cc: Vignesh R <vigneshr@ti.com>
Cc: Mugunthan V N <mugunthanvnm@ti.com>
Cc: Simon Glass <sjg@chromium.org>
Cc: Bin Meng <bmeng.cn@gmail.com>
Cc: Michal Simek <michal.simek@xilinx.com>
Cc: Siva Durga Prasad Paladugu <sivadur@xilinx.com>
Signed-off-by: NJagan Teki <jteki@openedev.com>

One macronix quad bit set using SR, it's good to
read back and check the written bit and also if
it's already been set check for the bit and return.

Cc: Vignesh R <vigneshr@ti.com>
Cc: Simon Glass <sjg@chromium.org>
Cc: Bin Meng <bmeng.cn@gmail.com>
Tested-by: NMugunthan V N <mugunthanvnm@ti.com>
Signed-off-by: NJagan Teki <jteki@openedev.com>

One spansion quad bit set using CR, it's good to
read back and check the written bit and also if
it's already been set check for the bit and return.

Cc: Vignesh R <vigneshr@ti.com>
Cc: Simon Glass <sjg@chromium.org>
Cc: Bin Meng <bmeng.cn@gmail.com>
Cc: Michal Simek <michal.simek@xilinx.com>
Cc: Siva Durga Prasad Paladugu <sivadur@xilinx.com>
Tested-by: NMugunthan V N <mugunthanvnm@ti.com>
Signed-off-by: NJagan Teki <jteki@openedev.com>

Setting up quad bit for micron devices need to do the
same way as other flash devices like spansion, winbond
etc does using enhanced volatile config register so this
patch adds this support instead of printing "QEB is volatile"

Cc: Simon Glass <sjg@chromium.org>
Cc: Bin Meng <bmeng.cn@gmail.com>
Cc: Peter Pan <peterpandong@micron.com>
Cc: Fabio Estevam <fabio.estevam@freescale.com>
Cc: Michal Simek <michal.simek@xilinx.com>
Cc: Siva Durga Prasad Paladugu <sivadur@xilinx.com>
Signed-off-by: NJagan Teki <jteki@openedev.com>

Used BIT macro like 1 << nr as BIT(nr) where nr is 0...n
Reviewed-by: NBin Meng <bmeng.cn@gmail.com>
Signed-off-by: NJagan Teki <jteki@openedev.com>

- Tab space
- Place all read commands at one place.
- Re-arrange write commands.
Reviewed-by: NBin Meng <bmeng.cn@gmail.com>
Signed-off-by: NJagan Teki <jteki@openedev.com>

Use direct call to device_remove instead of exctra
spi_flash_remove defination.
Reviewed-by: NSimon Glass <sjg@chromium.org>
Signed-off-by: NJagan Teki <jteki@openedev.com>

bar_end gives more meaningfull compared to bank_end and
spi_flash_write_bar uses bar_end so replaced bank_end with
bar_end in spi_flash_read_bar
Signed-off-by: NJagan Teki <jteki@openedev.com>

Since quad_mode functions are local to spi flash core,
rename them to a meaningful and readable names.
Signed-off-by: NJagan Teki <jteki@openedev.com>

Since spi_read_cmds_array is used locally in
spi_flash_scan, so move array to locally used
function instead of defining global array.
Tested-by: NJagan Teki <jteki@openedev.com>
Reviewed-by: NBin Meng <bmeng.cn@gmail.com>
Signed-off-by: NJagan Teki <jteki@openedev.com>

Since SPI_TX_* are spi_slave{} members so use spi protocol
notation instead spi flash programming, like

SPI_TX_BP  => SPI_TX_BYTE
SPI_TX_QPP => SPI_TX_QUAD

Cc: Simon Glass <sjg@chromium.org>
Tested-by: NJagan Teki <jteki@openedev.com>
Tested-by: NBin Meng <bmeng.cn@gmail.com>
Reviewed-by: NBin Meng <bmeng.cn@gmail.com>
Signed-off-by: NJagan Teki <jteki@openedev.com>

Used mode member from spi_slave{} instead of op_mode_tx.

Cc: Simon Glass <sjg@chromium.org>
Tested-by: NJagan Teki <jteki@openedev.com>
Tested-by: NBin Meng <bmeng.cn@gmail.com>
Reviewed-by: NBin Meng <bmeng.cn@gmail.com>
Signed-off-by: NJagan Teki <jteki@openedev.com>

Couldn't find the exact reason to define 'mode' for dm,
probably it is not using in non-dm drivers but it need
to visible both dm and non-dm as mode data is getting
dereferred in spi flash core ie common to both.

Cc: Simon Glass <sjg@chromium.org>
Tested-by: NJagan Teki <jteki@openedev.com>
Tested-by: NBin Meng <bmeng.cn@gmail.com>
Reviewed-by: NBin Meng <bmeng.cn@gmail.com>
Signed-off-by: NJagan Teki <jteki@openedev.com>

For better code readabilty, get the spi pointer from
spi_flash{} locally and use it instead of direct
dereferring spi pinter as flash->spi->*
Tested-by: NJagan Teki <jteki@openedev.com>
Tested-by: NBin Meng <bmeng.cn@gmail.com>
Reviewed-by: NBin Meng <bmeng.cn@gmail.com>
Signed-off-by: NJagan Teki <jteki@openedev.com>

Coverity notes that we do not ensure when we copy ifname we still have
space left to ensure NULL termination.  As cannot control the size of
ifr_name we must make sure that our argument will not overflow the
buffer.

Reported-by: Coverity (CID 131094)
Cc: Simon Glass <sjg@chromium.org>
Signed-off-by: NTom Rini <trini@konsulko.com>
Reviewed-by: NSimon Glass <sjg@chromium.org>

Some platforms need to ability to configure an offset to the standard
addresses extracted from the device-tree. This patch allows this by
adding a function to DM to configure this offset (if needed).
Signed-off-by: NStefan Roese <sr@denx.de>
Acked-by: NSimon Glass <sjg@chromium.org>
Cc: Simon Glass <sjg@chromium.org>
Fixed space before tab:
Signed-off-by: NSimon Glass <sjg@chromium.org>

Rather than using a new debug UART implementation, use the standard one
provided by U-Boot.
Signed-off-by: NSimon Glass <sjg@chromium.org>
Reviewed-by: NThomas Chou <thomas@wytron.com.tw>

Allow the ns16550 debug UART to be used without the full driver.
Signed-off-by: NSimon Glass <sjg@chromium.org>
Reviewed-by: NThomas Chou <thomas@wytron.com.tw>

In very very space-constrained devices even the full UART driver is too
large. In this case the debug UART can still be used in some cases.

Add options to enable the UART driver in SPL and U-Boot proper. Enable both
options by default.
Signed-off-by: NSimon Glass <sjg@chromium.org>
Reviewed-by: NThomas Chou <thomas@wytron.com.tw>

Adjust this driver to support driver model for Ethernet.
Signed-off-by: NSimon Glass <sjg@chromium.org>
Acked-by: NJoe Hershberger <joe.hershberger@ni.com>

Remove stamp data and create common functions for the main Ethernet
operations. This will make it easier to convert this driver to support
driver model.
Signed-off-by: NSimon Glass <sjg@chromium.org>
Acked-by: NJoe Hershberger <joe.hershberger@ni.com>

The current comments are confusing. We don't actually bind a generic device
when the device tree has no information. We try to scan available PCI
drivers. Update the comments to reflect this.
Signed-off-by: NSimon Glass <sjg@chromium.org>
Reviewed-by: NBin Meng <bmeng.cn@gmail.com>

At present pci_mmc_init() does not correctly use the PCI function since the
list it passes is not terminated. The array size passed to pci_mmc_init() is
actually not used correctly. Fix this and adjust the pci_mmc_init() to scan
all available MMC devices.

Adjust this code to use the new driver model PCI API.

This should move over to the new MMC uclass at some point.
Signed-off-by: NSimon Glass <sjg@chromium.org>
Reviewed-by: NBin Meng <bmeng.cn@gmail.com>