Thus far, the socfpga init code had hard-coded the configuration
of the ethernet PHY interface to RGMII in the ethernet registers
in sysmgr space, so PHYs connected in another modes did not work.

This patch fixes support for configurations where the ethernet PHYs
are connected over MII/GMII/RMII interfaces by parsing the phy-mode
OF property of the GMACs and configuring the ethernet registers in
sysmgr space accordingly.
Signed-off-by: NMarek Vasut <marex@denx.de>
Reported-by: NDenis Bakhvalov <denis.bakhvalov@nokia.com>
Cc: Dinh Nguyen <dinguyen@opensource.altera.com>

LS2080A is the primary SoC, and LS2085A is a personality with AIOP
and DPAA DDR. The RDB and QDS boards support both personality. By
detecting the SVR at runtime, a single image per board can support
both SoCs. It gives users flexibility to swtich SoC without the need
to reprogram the board.
Signed-off-by: NYork Sun <york.sun@nxp.com>
CC: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
Reviewed-by: NPrabhakar Kushwaha <prabhakar.kushwaha@nxp.com>

Signed-off-by: NGong Qianyu <Qianyu.Gong@nxp.com>
Reviewed-by: NYork Sun <york.sun@nxp.com>

Signed-off-by: NGong Qianyu <Qianyu.Gong@nxp.com>
Reviewed-by: NYork Sun <york.sun@nxp.com>

There is only one flash bank for ls1043aqds.
Signed-off-by: NWenbin Song <wenbin.song@nxp.com>
Reviewed-by: NYork Sun <york.sun@nxp.com>

This patch aims to fix the order of CSU slave index for the LS1021a
board.
Signed-off-by: NVincent Siles <vincent.siles@provenrun.com>
Reviewed-by: NAlison Wang <alison.wang@nxp.com>
Reviewed-by: NYork Sun <york.sun@nxp.com>

When switching between the early and final mmu tables, the stack will
get corrupted if the Non-Secure attribute is different.  For ls1043a,
this issue is currently masked because flush_dcache_all is called
before the switch when CONFIG_SYS_DPAA_FMAN is defined.
Signed-off-by: NEd Swarthout <Ed.Swarthout@nxp.com>
Reviewed-by: NYork Sun <york.sun@nxp.com>

When setting fixed-link property to DTS, the values should be converted
with using cpu_to_fdt32 so that to have correct value on little endian
Soc.
Signed-off-by: NShaohui Xie <Shaohui.Xie@nxp.com>
Reviewed-by: NYork Sun <york.sun@nxp.com>

Signed-off-by: NCodrin Ciubotariu <codrin.ciubotariu@nxp.com>
Acked-by: NJoe Hershberger <joe.hershberger@ni.com>
Reviewed-by: NYork Sun <york.sun@nxp.com>

Some SerDes protocols might not enable all l2switch ports. In this case,
these ports should not be configured to perform Rx/Tx operations.
This also fixes an issue when flooded frames were also switched to
disabled ports and frames start to accumulate, consuming memory
and eventually causing head-of-line blocking for other frames.
Signed-off-by: NCodrin Ciubotariu <codrin.ciubotariu@nxp.com>
Acked-by: NJoe Hershberger <joe.hershberger@ni.com>
Reviewed-by: NYork Sun <york.sun@nxp.com>

We can use phys_addr_to for esdhc_base to discard
the #ifdef.
Signed-off-by: NPeng Fan <van.freenix@gmail.com>
Cc: York Sun <york.sun@nxp.com>
Cc: Yangbo Lu <yangbo.lu@nxp.com>
Cc: Eric Nelson <eric@nelint.com>
Cc: Fabio Estevam <fabio.estevam@nxp.com>
Cc: Pantelis Antoniou <panto@antoniou-consulting.com>
Cc: Tom Rini <trini@konsulko.com>
Reviewed-by: NTom Rini <trini@konsulko.com>
Reviewed-by: NYork Sun <york.sun@nxp.com>

Support Driver Model for fsl esdhc driver.

1. Introduce a new structure struct fsl_esdhc_priv
2. Refactor fsl_esdhc_initialize which is originally used by board code.
   - Introduce fsl_esdhc_init to be common usage for DM and non-DM
   - Introduce fsl_esdhc_cfg_to_priv to build the bridge for non-DM part.
   - The original API for board code is still there, but we use
     'fsl_esdhc_cfg_to_priv' and 'fsl_esdhc_init' to serve it.
3. All the functions are changed to use 'struct fsl_esdhc_priv', except
   fsl_esdhc_initialize.
4. Since clk driver is not implemented, use mxc_get_clock to geth
   the clk and fill 'priv->sdhc_clk'.

Has been tested on i.MX6UL 14X14 EVK board:
"
=>dm tree
....
 simple_bus  [ + ]    |   `-- aips-bus@02100000
  mmc        [ + ]    |       |-- usdhc@02190000
  mmc        [ + ]    |       |-- usdhc@02194000
....
=> mmc list
FSL_SDHC: 0 (SD)
FSL_SDHC: 1 (SD)
"
Signed-off-by: NPeng Fan <van.freenix@gmail.com>
Cc: York Sun <york.sun@nxp.com>
Cc: Yangbo Lu <yangbo.lu@nxp.com>
Cc: Hector Palacios <hector.palacios@digi.com>
Cc: Eric Nelson <eric@nelint.com>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Fabio Estevam <fabio.estevam@nxp.com>
Cc: Pantelis Antoniou <panto@antoniou-consulting.com>
Cc: Simon Glass <sjg@chromium.org>
Tested-By: NEric Nelson <eric@nelint.com>
Reviewed-by: NYork Sun <york.sun@nxp.com>

Claim the MPP pins for the NAND flash controller only when it's actually
being used. This allows the pins to be shared with the SPI interface
which already supports an equivalent on-access MPP reconfiguration.
Reviewed-by: NMark Tomlinson <mark.tomlinson@alliedtelesis.co.nz>
Signed-off-by: NChris Packham <judge.packham@gmail.com>
Acked-by: NScott Wood <oss@buserror.net>
Signed-off-by: NStefan Roese <sr@denx.de>

Currently only chip-select 0 is supported by the kirkwood SPI driver.
The Armada XP / 38x SoCs also use this driver and support multiple chip
selects. This patch adds support for multiple CS on MVEBU.

The register definitions are restructured a bit with this patch. Grouping
them to the corresponding registers.
Signed-off-by: NStefan Roese <sr@denx.de>
Cc: Luka Perkov <luka.perkov@sartura.hr>
Reviewed-by: NJagan Teki <jteki@openedev.com>

Enable EFI partition support for ZynqMP.
Signed-off-by: NMichal Simek <michal.simek@xilinx.com>

PCS auto negotaiation bit should be enabled
along with SGMII autonegotation enabled
in phy.
Signed-off-by: NSiva Durga Prasad Paladugu <sivadur@xilinx.com>
Signed-off-by: NMichal Simek <michal.simek@xilinx.com>

Add support of SGMII to TI phy dp838367
Enable the SGMII and PCS settings in phy
control, CFG2 and BIST registers
Signed-off-by: NSiva Durga Prasad Paladugu <sivadur@xilinx.com>
Signed-off-by: NMichal Simek <michal.simek@xilinx.com>

Return error from probe in case of invalid phy address.
This fixes the issue of uboot crash if phy is not detected.
Signed-off-by: NSiva Durga Prasad Paladugu <sivadur@xilinx.com>
Signed-off-by: NMichal Simek <michal.simek@xilinx.com>

preboot macro load the uEnv.txt from mmc 0 when bootmode is mmc. uenvcmd is
executed after load of uEnv.txt if it is defined in the uEnv.txt env text
file.

The default importbootenv macro reads the uEnv.txt from mmc.

Additional to this, usb_loadbootenv is added to support loading uEnv.txt
from usb dev 0.
Signed-off-by: NJason Wu <jason.wu.misc@gmail.com>
Signed-off-by: NMichal Simek <michal.simek@xilinx.com>

Enable FLASH_BAR for these targets to be in sync with all zynq boards.
Signed-off-by: NMichal Simek <michal.simek@xilinx.com>

Initial Ceva Sata init code.
Signed-off-by: NMichal Simek <michal.simek@xilinx.com>
Reviewed-by: NTom Rini <trini@konsulko.com>

Handle all Xilinx ZynqMP boards with one fragment.
Signed-off-by: NMichal Simek <michal.simek@xilinx.com>

Read information about memory from DT. This patch simplify life with
synchronization between DT and board files.

dram_init() only needs maximum RAM size below 4GB that's why please sort
banks in memory node.
dram_init_banksize() copies memory setup to bi_dram[].
This will avoid reading information from DT twice.

Memory test start/end were changed to DDR location to let memtest still
compiled.
Signed-off-by: NMichal Simek <michal.simek@xilinx.com>

Simplify board config file.
Signed-off-by: NMichal Simek <michal.simek@xilinx.com>

This option enable adding new platform suport just by adding defconfig
and DTS file which will target generic configuration for SoC.
Make no sense to extend Kconfig just create a pointer between DTS and
configuration file.
Signed-off-by: NMichal Simek <michal.simek@xilinx.com>

Enabling writing files to FAT and EXT4 for USB.
Signed-off-by: NMichal Simek <michal.simek@xilinx.com>

Synchronize it with zynq platform.
Signed-off-by: NSoren Brinkmann <soren.brinkmann@xilinx.com>
Signed-off-by: NMichal Simek <michal.simek@xilinx.com>

Do not use debug() when printing error message. Use printf instead.
Signed-off-by: NMichal Simek <michal.simek@xilinx.com>

OF_CONTROL is enabled by default that's why this is dead code.
Signed-off-by: NMichal Simek <michal.simek@xilinx.com>

Read information about timer and interrupts from DT. This is the first
small step to move timer and intc to DM.
Signed-off-by: NMichal Simek <michal.simek@xilinx.com>

There is incorrect setting for USB which didn't work with origin
ps7_init_gpl.X files.
Use default setting for Digilent Zybo projects with HDMI in PL.
Signed-off-by: NMichal Simek <monstr@monstr.eu>
Signed-off-by: NMichal Simek <michal.simek@xilinx.com>

Zybo has on board I2C EEPROM which contains preprogrammed MAC address.
Signed-off-by: NMichal Simek <monstr@monstr.eu>
Signed-off-by: NMichal Simek <michal.simek@xilinx.com>

Provide board specific option how to read MAC address from ROM.
Do it in generic way to be reusable by differnet boards.
If this is not enough board specific functions can be created.

Signed-off-by: Joe Hershberger <joe.hershberger@gmail.com> # driver part
Signed-off-by: NMichal Simek <monstr@monstr.eu>
Signed-off-by: NMichal Simek <michal.simek@xilinx.com>

Enable overwriting variables out of main config file.
Signed-off-by: NMichal Simek <michal.simek@xilinx.com>

In SGMII cases the isolate bit might set after DMA and
ethernet resets and hence check and clear during
setup_phy if it was set.
Signed-off-by: NSiva Durga Prasad Paladugu <sivadur@xilinx.com>
Acked-by: NJoe Hershberger <joe.hershberger@ni.com>
Signed-off-by: NMichal Simek <michal.simek@xilinx.com>

Pass appropriate interface type to phy_connect
instead of zero.
Signed-off-by: NSiva Durga Prasad Paladugu <sivadur@xilinx.com>
Acked-by: NJoe Hershberger <joe.hershberger@ni.com>
Signed-off-by: NMichal Simek <michal.simek@xilinx.com>

Add support of Xilinx PCS/PMA core phy for Zynq
Signed-off-by: NSiva Durga Prasad Paladugu <sivadur@xilinx.com>
Signed-off-by: NMichal Simek <michal.simek@xilinx.com>

Add support of SGMII interface for zynq GEM.
Read xlnx,emio property from DT.
Signed-off-by: NSiva Durga Prasad Paladugu <sivadur@xilinx.com>
Signed-off-by: NMichal Simek <michal.simek@xilinx.com>