- 18 9月, 2003 2 次提交
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由 wdenk 提交于
- fix spelling errors - set GD_FLG_DEVINIT flag only after device function pointers are valid - Allow CFG_ALT_MEMTEST on systems where address zero isn't writeable - enable 3.rd UART (ST-UART) on PXA(XScale) CPUs - trigger watchdog while waiting in serial driver
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由 wdenk 提交于
Minor cleanup of comments
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- 17 9月, 2003 6 次提交
- 16 9月, 2003 3 次提交
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由 wdenk 提交于
go back to 66 MHz for stability
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由 wdenk 提交于
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由 wdenk 提交于
- add description for missing CFG_CMD_* entries in the README file - sacsng tweaks: include/configs/sacsng.h: + Support extra bootp options like: 2nd DNS and send hostname + Enabling ping and irq command + Adding defines for a bunch of misc configrabled options (patches for these options will be coming) + Adding watchdog support, but it isn't enabled yet. board/sacsng/sacsng.c: + Suppressing unneeded output when the quiet environment is non-zero. + show_boot_progress() now accepts any negative number as a failure code. + show_boot_progress() flashes the error code 5 times, and then resets the board to retry the boot from the top * Patch by Gleb Natapov, 14 Sep 2003: enable watchdog support for all MPC824x boards that have a watchdog
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- 15 9月, 2003 1 次提交
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由 wdenk 提交于
enable watchdog support for all MPC824x boards that have a watchdog * On MPC5200, restrict FEC to a maximum of 10 Mbps to work around the "Non-octet Aligned Frame" errors we see at 100 Mbps * Patch by Sharad Gupta, 14 Sep 2003: fix SPR numbers for upper BAT register ([ID]BAT[4-7][UL])
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- 14 9月, 2003 2 次提交
- 13 9月, 2003 1 次提交
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由 wdenk 提交于
Changed default memory option on MPC8266ADS to NOT be Page Based Interleave, since this doesn't work very well with the standard 16MB DIMM * Patch by George G. Davis, 12 Sep 2003: fix Makefile settings for sk98 driver
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- 12 9月, 2003 18 次提交
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由 wdenk 提交于
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由 stroese 提交于
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由 stroese 提交于
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由 stroese 提交于
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由 stroese 提交于
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由 stroese 提交于
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由 stroese 提交于
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由 stroese 提交于
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由 stroese 提交于
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由 stroese 提交于
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由 stroese 提交于
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由 stroese 提交于
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由 stroese 提交于
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由 stroese 提交于
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由 stroese 提交于
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由 stroese 提交于
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由 wdenk 提交于
add burn-in tests for TRAB board * Enable instruction cache on MPC5200 board
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由 wdenk 提交于
- allow for longer timeouts for USB mass storage devices * Patch by Denis Peter, 11 Sep 2003: - fix USB data pointer assignment for bulk only transfer. - prevent to display erased directories in FAT filesystem. * Change output format for NAND flash - make it look like for other memory, too
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- 11 9月, 2003 2 次提交
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由 wdenk 提交于
add FAT support for IDE, SCSI and USB * Patches by Gleb Natapov, 2 Sep 2003: - cleanup of POST code for unsupported architectures - MPC824x locks way0 of data cache for use as initial RAM; this patch unlocks it after relocation to RAM and invalidates the locked entries. * Patch by Gleb Natapov, 30 Aug 2003: new I2C driver for mpc107 bridge. Now works from flash. * Patch by Dave Ellis, 11 Aug 2003: - JFFS2: fix typo in common/cmd_jffs2.c - JFFS2: fix CFG_JFFS2_SORT_FRAGMENTS option - JFFS2: remove node version 0 warning - JFFS2: accept JFFS2 PADDING nodes - SXNI855T: add AM29LV800 support - SXNI855T: move environment from EEPROM to flash - SXNI855T: boot from JFFS2 in NOR or NAND flash * Patch by Bill Hargen, 11 Aug 2003: fixes for I2C on MPC8240 - fix i2c_write routine - fix iprobe command - eliminates use of global variables, plus dead code, cleanup.
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由 wdenk 提交于
(tested with USB memory sticks only) * Avoid flicker on TRAB's VFD
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- 06 9月, 2003 1 次提交
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由 wdenk 提交于
* Add PCI support for SL8245 board * Support IceCube board configurations with 1 x AMD AM29LV065 (8 MB) or 1 x AM29LV652 (two LV065 in one chip = 16 MB); Run IPB at 133 Mhz; adjust the MII clock frequency accordingly * Set BRG_CLK on PM825/826 to 64MHz (VCO_OUT / 4, instead of 16 MHz) to allow for more accurate baudrate settings (error now 0.7% at 115 kbps, instead of 3.5% before) * Patch by Andreas Mohr, 4 Sep 2003: Fix a lot of spelling errors
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- 03 9月, 2003 3 次提交
- 01 9月, 2003 1 次提交
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由 wdenk 提交于
According to the MPC8260 User's Manual, PCI_MODE signal should be reflected in SCCR register, and local bus pins configuration is taken from HRCW and appears in SIUMCR. For some reason it does not work this way, so the only possibility to detect if the board is configured in PCI mode is to check the BCSR. This patch sets SCCR and SIUMCR according to the BCSR.
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