- 11 1月, 2008 1 次提交
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由 Niklaus Giger 提交于
vxWorks expects in TLB 0 a entry for the Machine Check interrupt TLB 1 a entry for the RAM TLB 2 a entry for the EBC TLB 3 a entry for the boot flash After changing the baudrate to 9600 I had no problems to boot the vxWorks image as distributed by WindRiver (Revision 2.0/1 from June 18, 2007) Signed-off-by: NNiklaus Giger <niklaus.giger@netstal.com>
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- 04 1月, 2008 1 次提交
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由 Lawrence R. Johnson 提交于
Note: this patch changes the configuration of some GPIO registers: Register Old Value New Value --------------- ---------- ---------- DCR GPIO0_TCR 0x0000000F 0x0000F0CF DCR GPIO0_TSRH 0x55005000 0x00000000 DCR GPIO1_TCR 0xC2000000 0xE2000000 DCR GPIO1_TSRL 0x0C000000 0x00200000 DCR GPIO1_ISR2L 0x00050000 0x00110000 Signed-off-by: NLarry Johnson <lrj@acm.org>
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- 28 12月, 2007 4 次提交
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由 Stefan Roese 提交于
On Sequoia & LWMON5 the virtual address of the POST cache test is now moved to a bigger address. This enables usage of more memory on those boards. Signed-off-by: NStefan Roese <sr@denx.de>
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由 Stefan Roese 提交于
Now the cpu node setup ("timebase-frequency" and "clock-frequency") is without using the absolute path to the cpu node. This makes it possible to use this U-Boot version with both versions of cpu-node naming "cpu@0" and the former "PowerPC,440EPx@0". Signed-off-by: NStefan Roese <sr@denx.de>
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由 Markus Klotzbücher 提交于
When using dhcp/bootp the "netmask" environment variable is not set because CONFIG_BOOTP_SUBNETMASK is not defined. But usually this is desireable, so the following patch adds this this option to the board config. Signed-off-by: NMarkus Klotzbuecher <mk@denx.de> Signed-off-by: NStefan Roese <sr@denx.de>
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由 Stefan Roese 提交于
This patch update the 4xx fdt support. It enabled fdt booting on the AMCC Kilauea and Sequoia for now. More can follow later quite easily. Signed-off-by: NStefan Roese <sr@denx.de>
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- 13 12月, 2007 1 次提交
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由 Stefan Roese 提交于
This patch update the 4xx fdt support. It enabled fdt booting on the AMCC Kilauea and Sequoia for now. More can follow later quite easily. Signed-off-by: NStefan Roese <sr@denx.de>
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- 09 11月, 2007 1 次提交
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由 Matthias Fuchs 提交于
This patch makes the sequoia board use the generic usb-ohci driver instead of cpu/ppc4xx/usb_ohci.c. Signed-off-by: NMatthias Fuchs <matthias.fuchs@esd-electronics.com> Signed-off-by: NStefan Roese <sr@denx.de>
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- 01 11月, 2007 1 次提交
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由 Stefan Roese 提交于
All 4xx board config files don't need the cache definitions anymore. These are now defined in common headers. Signed-off-by: NStefan Roese <sr@denx.de>
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- 15 10月, 2007 1 次提交
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由 Stefan Roese 提交于
The BCSR status bit for the 66MHz PCI operation was correctly addressed (MSB/LSB problem). Now the correct currently setup PCI frequency is displayed upon bootup. This patch also fixes this problem on Rainier & Yellowstone, since these boards use the same souce code as Sequoia & Yosemite do. Signed-off-by: NStefan Roese <sr@denx.de>
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- 31 8月, 2007 1 次提交
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由 Gary Jennejohn 提交于
The 440EPx has a problem when the PCI_CACHE_LINE_SIZE register is set to non-zero, because it doesn't support MRM (memory-read- multiple) correctly. We now added the possibility to configure this register in the board config file, so that the default value of 8 can be overridden. Here the details of this patch: o drivers_pci_auto.c: introduce CFG_PCI_CACHE_LINE_SIZE to allow board-specific settings. As an example the sequoia board requires 0. Idea from Stefan Roese <sr@denx.de>. o board/amcc/sequoia/init.S: add a TLB mapping at 0xE8000000 for the PCI IO-space. Obtained from Stefan Roese <sr@denx.de>. o include/configs/sequoia.h: turn CONFIG_PCI_PNP back on and set CFG_PCI_CACHE_LINE_SIZE to 0. Signed-off-by: NGary Jennejohn <garyj@denx.de> Signed-off-by: NStefan Roese <sr@denx.de>
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- 16 8月, 2007 1 次提交
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由 Stefan Roese 提交于
Signed-off-by: NStefan Roese <sr@denx.de>
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- 10 7月, 2007 1 次提交
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由 Jon Loeliger 提交于
Explicitly add in default CONFIG_BOOTP_* options where cmd_confdefs.h used to be included but CONFIG_BOOTP_MASK was not defined. Remove lingering references to CFG_CMD_* symbols. Signed-off-by: NJon Loeliger <jdl@freescale.com>
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- 05 7月, 2007 2 次提交
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由 Jon Loeliger 提交于
Signed-off-by: NJon Loeliger <jdl@freescale.com>
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由 Sergei Poselenov 提交于
Signed-off-by: NSergei Poselenov <sposelenov@emcraft.com>
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- 25 6月, 2007 1 次提交
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由 Stefan Roese 提交于
This patch removes the CFG_PCI_PRE_INIT option completely, since it's not needed anymore with the patch from Matthias Fuchs with the "weak" pci_pre_init() implementation. Signed-off-by: NStefan Roese <sr@denx.de>
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- 23 6月, 2007 2 次提交
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由 Wolfgang Denk 提交于
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由 Igor Lisitsin 提交于
Added memory, CPU, UART, I2C and SPR POST tests for PPC440. Signed-off-by: NIgor Lisitsin <igor@emcraft.com> --
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- 15 6月, 2007 1 次提交
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由 Grzegorz Bernacki 提交于
- Introduced dedicated switches for building 440 and 405 images required for 440-specific machine instructions like 'rfmci' etc. - Exception vectors moved to the proper location (_start moved away from the critical exception handler space, which it occupied) - CriticalInput now serviced (with default handler) - MachineCheck properly serviced (added a dedicated handler and return subroutine) - Overall cleanup of exceptions declared with STD_EXCEPTION macro (unused, unhandled and those not relevant for 4xx were eliminated) - Eliminated Linux leftovers, removed dead code Signed-off-by: NGrzegorz Bernacki <gjb@semihalf.com> Signed-off-by: NRafal Jaworowski <raj@semihalf.com> Signed-off-by: NStefan Roese <sr@denx.de>
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- 01 6月, 2007 1 次提交
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由 Stefan Roese 提交于
Signed-off-by: NStefan Roese <sr@denx.de>
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- 08 5月, 2007 1 次提交
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由 Jeffrey Mann 提交于
A '3' got cut off in the formatting of the last patch to automatically change the clock speed of the system clock on sequoia board. Signed-off-by: NJeffrey Mann <mannj@embeddedplanet.com> Signed-off-by: NStefan Roese <sr@denx.de>
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- 05 5月, 2007 1 次提交
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由 Jeffrey Mann 提交于
The AMCC Secquoia board has been changed in a new revision from using a 33.000 MHz clock to a 33.333 MHz system clock. A bit in the CPLD indicates the difference. This patch reads that bit and uses the correct clock speed for the board. This code is backward compatable will all prior boards. All prior boards will be read as 33.000. Signed-off-by: NJeffrey Mann <mannj@embeddedplanet.com> Signed-off-by: NStefan Roese <sr@denx.de>
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- 28 3月, 2007 1 次提交
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由 Stefan Roese 提交于
Signed-off-by: NStefan Roese <sr@denx.de>
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- 24 3月, 2007 1 次提交
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由 Stefan Roese 提交于
Signed-off-by: NStefan Roese <sr@denx.de>
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- 19 2月, 2007 1 次提交
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由 Stefan Roese 提交于
As spotted by Matthias Fuchs, the READY input should not be enabled for the NOR FLASH on the Sequoia board. Signed-off-by: NStefan Roese <sr@denx.de>
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- 01 2月, 2007 1 次提交
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由 Stefan Roese 提交于
When PCI PNP is enabled the pci pnp configuration routine is called which sets the PCI_CACHE_SIZE_LINE to 8. This seems to generate some problems with some PCI cards. For now disable the PCI PNP configuration. Signed-off-by: NStefan Roese <sr@denx.de>
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- 31 1月, 2007 1 次提交
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由 Stefan Roese 提交于
The config file now handles the 2nd target, the Rainier (440GRx) evaluation board better. Additionally the PPC input clock was adjusted to match the correct value of 33.0 MHz. Signed-off-by: NStefan Roese <sr@denx.de>
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- 05 1月, 2007 1 次提交
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由 Stefan Roese 提交于
This code will optimize the DDR2 controller setup on a board specific basis. Note: This code doesn't work right now on the NAND booting image for the Sequoia board, since it doesn't fit into the 4kBytes for the SPL image. Signed-off-by: NStefan Roese <sr@denx.de>
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- 28 11月, 2006 1 次提交
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由 Stefan Roese 提交于
The current NAND Bootloader setup forces the environment variables to be in line with the bootloader. This change enables the configuration to be made in the board include file instead so that it can be individually enabled. Signed-off-by: NNick Spence <nick.spence@freescale.com> Signed-off-by: NStefan Roese <sr@denx.de>
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- 21 11月, 2006 1 次提交
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由 Stefan Roese 提交于
Signed-off-by: NStefan Roese <sr@denx.de>
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- 20 10月, 2006 1 次提交
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由 Stefan Roese 提交于
Based on idea and implementation from Jeff Mann Patch by Stefan Roese, 20 Oct 2006
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- 13 9月, 2006 2 次提交
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由 Stefan Roese 提交于
Patch by Stefan Roese, 13 Sep 2006
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由 Stefan Roese 提交于
Patch by Stefan Roese, 12 Sep 2006
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- 07 9月, 2006 1 次提交
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由 Stefan Roese 提交于
- Add support for PPC440EPx & PPC440GRx - Add support for PPC440EP(x)/GR(x) NAND controller in cpu/ppc4xx directory - Add NAND boot functionality for Sequoia board, please see doc/README.nand-boot-ppc440 for details - This Sequoia NAND image doesn't support environment in NAND for now. This will be added in a short while. Patch by Stefan Roese, 07 Sep 2006
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