The Default mode that is built for the Davinci DVEVM happens
to be the NOR mode.
When we want to build for the NAND mode, we get a compilation
error. This is overcome by defining the CONFIG_MTD_DEVICE
flag in the NAND mode.
The image built for NAND mode was successfully tested on the
DaVinci DM6446 EVM.
Signed-off-by: NSandeep Paulraj <s-paulraj@ti.com>

v7_flush_dcache_all, because it depends on omap ROM code is not
generic.  Rename the function to 'invalidate_dcache' and move it
to the omap cpu directory.

Collect the other omap cache routines l2_cache_enable and
l2_cache_disable with invalide_dcache into cache.S.  This
means removing the old cache.c file that contained l2_cache_enable
and l2_cache_disable.

The conversion from cache.c to cache.S was done most through
disassembling the uboot binary.  The only significant change was
to change the comparision for the return of get_cpu_rev from

   cmp	r0, #0
   beq	earlier_than_label

Which was lost information to

   cmp	r0, #CPU_3XX_ES20
   blt	earlier_than_label

The paths through the enable routine were verified by
adding an infinite loop and seeing the hang.  Then
removing the infinite loop and seeing it continue.

The disable routine is similar enough that it was not
tested with this method.

Run tested by cold booting from nand on beagle and zoom1.
Compile tested on MAKEALL arm.
Signed-off-by: NTom Rix <Tom.Rix@windriver.com>

This patch removes the asm/sizes.h header file from being
included in the DaVinci SOC configs.
References to SZ_xx have been replaced by appropriate
bit shifted values.
Signed-off-by: NSandeep Paulraj <s-paulraj@ti.com>
Acked-by: NWolfgang Denk <wd@denx.de>

Forcing the tables into got2 caused extra relocation when using -mrelocatable.
This patch requires any board defining CONFIG_BIOSEMU to use -mrelocatable.
Signed-off-by: NEd Swarthout <Ed.Swarthout@freescale.com>
Acked-by: NJin Zhengxiong <Jason.Jin@freescale.com>

Signed-off-by: NLuigi 'Comio' Mantellini <luigi.mantellini@idf-hit.com>
Signed-off-by: NBen Warren <biggerbadderben@gmail.com>

Signed-off-by: NLuigi 'Comio' Mantellini <luigi.mantellini@idf-hit.com>
Signed-off-by: NBen Warren <biggerbadderben@gmail.com>

Rewrite the miiphybb (Bit-banged MII bus driver) in order to support an arbitrary number of mii buses.

This feature is useful when your board uses different mii buses for different
phys and all (or a part) of these buses are implemented via bit-banging mode.

The driver requires that the following macros should be defined into the board
configuration file:

CONFIG_BITBANGMII       - Enable the miiphybb driver
CONFIG_BITBANGMII_MULTI - Enable the multi bus support

If the CONFIG_BITBANGMII_MULTI is not defined, the board's config file needs
to define at least the following macros:

MII_INIT      - Generic code to enable the MII bus (optional)
MDIO_DECLARE  - Declaration needed to access to the MDIO pin (optional)
MDIO_ACTIVE   - Activate the MDIO pin as out pin
MDIO_TRISTATE - Activate the MDIO pin as input/tristate pin
MDIO_READ     - Read the MDIO pin
MDIO(v)       - Write v on the MDIO pin
MDC_DECLARE   - Declaration needed to access to the MDC pin (optional)
MDC(v)        - Write v on the MDC pin

The previous macros make the driver compatible with the previous version
(that didn't support the multi-bus).

When the CONFIG_BITBANGMII_MULTI is also defined, the board code needs to fill
the bb_miiphy_buses[] array with a record for each required bus and declare
the bb_miiphy_buses_num variable with the number of mii buses.
The record (struct bb_miiphy_bus) has the following fields/callbacks (see
miiphy.h for details):

char name[]            - The symbolic name that must be equal to the MII bus
                         registered name
int (*init)()          - Initialization function called at startup time (just
                         before the Ethernet initialization)
int (*mdio_active)()   - Activate the MDIO pin as output
int (*mdio_tristate)() - Activate the MDIO pin as input/tristate pin
int (*set_mdio)()      - Write the MDIO pin
int (*get_mdio)()      - Read the MDIO pin
int (*set_mdc)()       - Write the MDC pin
int (*delay)()         - Delay function
void *priv             - Private data used by board specific code

The board code will look like:

struct bb_miiphy_bus bb_miiphy_buses[] = {
 { .name = miibus#1, .init = b1_init, .mdio_active = b1_mdio_active, ... },
 { .name = miibus#2, .init = b2_init, .mdio_active = b2_mdio_active, ... },
 ...
int bb_miiphy_buses_num = sizeof(bb_miiphy_buses) /
                          sizeof(bb_miiphy_buses[0]);
Signed-off-by: NLuigi 'Comio' Mantellini <luigi.mantellini@idf-hit.com>
Signed-off-by: NBen Warren <biggerbadderben@gmail.com>

NULL is an absolute value and should not be relocated.
After this correction code like:
 void weak_fun(void) __attribute__((weak));
 printf("weak_fun:%p\n", weak_fun);
will still print null after relocation.
Signed-off-by: NJoakim Tjernlund <Joakim.Tjernlund@transmode.se>

When U-Boot is relocated from flash to RAM pointers are modified
accordingly.  However, pointers initialzed with NULL values should not
be modified so that they maintain their intended NULL value.  If the
BSS segment is linked at address 0 its address will not be
updated as necessary during relocation.

This is a temporary workaround.  The end goal is to add support to
U-Boot to dynamically locate the BSS at an arbitrary address at
runtime.  When the ability to fixup the BSS inteligently is
added, this workaround can be removed and the 85xx link script
can put the BSS at a fixed address at link time.
Signed-off-by: NPeter Tyser <ptyser@xes-inc.com>

This fixes the code and the comment according to the original intent of
doing an intensive memory test when PSC6_3 is pulled low on the STK52xx.
Notably PORT_CONFIG will be overridden with this correct code now,
so beware.

The original code only worked by coincidence depending on the PORT_CONFIG
setting from the header file.  The new code was tested to ensure that the
(undocumented) memory test still works on the STK52x.
Signed-off-by: NDetlev Zundel <dzu@denx.de>
CC: Martin Krause <Martin.Krause@tqs.de>

Minor white-space cleanup.
Signed-off-by: NWolfgang Denk <wd@denx.de>

Commit 054197ba and later fixes used an array to initialize some of
the MDDRC parameters; however, the use of an array turned out to be a
bad idea as it was not possible to correlate structure entries to
array indices in readable and reliable way. Now we use a struct
instead, which makes this self-explanatory.
Signed-off-by: NWolfgang Denk <wd@denx.de>

After running checkstyle.pl on the three previous patches I noted that in
the *.h files there were a lot of long lines. This patch solves this problem.
Signed-off-by: NNiklaus Giger <niklaus.giger@member.fsf.org>
Signed-off-by: NStefan Roese <sr@denx.de>

The command "reginfo" got an overhaul for the ppc4xx. It dumps all the
relevant HW configuration registers (address, symbolic name, content).
This allows to easily detect errors in *.h files and changes in the HW
configuration.
Signed-off-by: NNiklaus Giger <niklaus.giger@member.fsf.org>
Signed-off-by: NStefan Roese <sr@denx.de>

Modify all existing *.c files to use the new register names
as seen in the AMCC manuals.
Signed-off-by: NNiklaus Giger <niklaus.giger@member.fsf.org>
Signed-off-by: NStefan Roese <sr@denx.de>

Here you find all the changes in the include directory for new register names
and adapting other ones to the names used by AMCC in their manuals, e.g.
For 440EPx/GRPPC440EPx/GRX, Revision 1.15 – September 22, 2008
For PPC405GP Embedded Processor, Revision 1.02 – March 22, 2006
Signed-off-by: NNiklaus Giger <niklaus.giger@member.fsf.org>
Signed-off-by: NStefan Roese <sr@denx.de>

Unfortunately some Rev D PPC405EX/405EXr PVR's are identical with older
405EX(r) parts. Here a list:

0x12911475 - 405EX Rev D with Security *and* 405EX Rev A/B witout Sec
0x12911473 - 405EX Rev D without Security *and* 405EXr Rev A/B with Sec

Since there are only a few older parts in the field, this patch now
changes the PVR's above to represent the new Rev D versions.
Signed-off-by: NStefan Roese <sr@denx.de>
Cc: Phong Vo" <pvo@amcc.com>

This message is printed upon PCIe bus scan, not only upon error, but also
if no PCIe device is detected at all. Since this is not an error, let's
remove this message in this case. We already have the message
"link is not up." if there is no PCIe device present.
Signed-off-by: NStefan Roese <sr@denx.de>
Acked-by: NWolfgang Denk <wd@denx.de>

The SPD detection code for the Denali memory controller used on some
ppc4xx
processors incorrectly encodes DDR0_42. With certain memory
configurations,
this can cause the bootwrapper to incorrectly calculate the installed
memory
size, because the number of row bits is wrong. This patch fixes that
encoding.
Signed-off-by: NMike Nuss <mike@terascala.com>
Signed-off-by: NStefan Roese <sr@denx.de>

As discussed on mailing list, <0 indicates failure, >=0 indicates number
of interfaces found.

Also added blurb about private data
Signed-off-by: NBen Warren <biggerbadderben@gmail.com>

Signed-off-by: NMike Frysinger <vapier@gentoo.org>
Acked-by: NWolfgang Denk <wd@denx.de>
Signed-off-by: NBen Warren <biggerbadderben@gmail.com>

if link up detection code is disabled through config option, it gives build warning.
This patch fixes the same
Signed-off-by: NPrafulla Wadaskar <prafulla@marvell.com>
Signed-off-by: NBen Warren <biggerbadderben@gmail.com>

All in-tree boards that use this controller have CONFIG_NET_MULTI
added
Also:
  - changed CONFIG_DRIVER_SMC91111 to CONFIG_SMC91111
  - cleaned up line lengths
  - modified all boards that override weak function in this driver
  - modified all eeprom standalone apps to work with new driver
  - updated blackfin standalone EEPROM app after testing
Signed-off-by: NBen Warren <biggerbadderben@gmail.com>
Signed-off-by: NMike Frysinger <vapier@gentoo.org>

following build warning was observed

mv88e61xx.c: In function ‘mv88e61xx_busychk’:
mv88e61xx.c:208: warning: dereferencing type-punned pointer will break strict-aliasing rules

This patch fixes the same
Patch tested for rd6281a board build
Signed-off-by: NPrafulla Wadaskar <prafulla@marvell.com>
Signed-off-by: NBen Warren <biggerbadderben@gmail.com>

On 405EZ the RX-/TX-interrupts are coalesced into one IRQ bit in the
UIC. We need to acknowledge the RX-/TX-interrupts in the
SDR0_ICINTSTAT reg as well.

This problem was introduced with commit
d1631fe1 [ppc4xx: Consolidate PPC4xx UIC defines]
Signed-off-by: NJames Clough <james@rtetc.com>
Signed-off-by: NStefan Roese <sr@denx.de>
Signed-off-by: NBen Warren <biggerbadderben@gmail.com>

The random_port() is meant to be used by other net code, but without a
prototype, we get fun warnings like:
dns.c: In function 'DnsSend':
dns.c:89: warning: implicit declaration of function 'random_port'
Signed-off-by: NMike Frysinger <vapier@gentoo.org>
Signed-off-by: NBen Warren <biggerbadderben@gmail.com>

Now that proper relocation is supported, the reloc_off field is no longer
necessary.

Note that the location of the standalone application jump table pointer
in the global data structure is affected by this change, breaking
execution of standalone applications compiled for previous versions of
U-Boot.

We therefore increment XF_VERSION to 6
Signed-off-by: NPeter Tyser <ptyser@xes-inc.com>
Signed-off-by: NWolfgang Denk <wd@denx.de>

These architectures don't need relocation fixups, so reduce their
codesize a bit by defining CONFIG_RELOC_FIXUP_WORKS.

Also remove the reloc_off field from their global data structures
as it is no longer needed.

Note that the location of the standalone application jump table pointer
in the global data structure is affected by this change, breaking
execution of standalone applications compiled for previous versions of
U-Boot. We will therefore increment XF_VERSION in the next commit,
which also touches this area.
Signed-off-by: NPeter Tyser <ptyser@xes-inc.com>
Signed-off-by: NWolfgang Denk <wd@denx.de>

Add #ifdefs where necessary to not perform relocation fixups.  This
allows boards/architectures which support relocation to trim a decent
chunk of code.

Note that this patch doesn't add #ifdefs to architecture-specific code
which does not support relocation.
Signed-off-by: NPeter Tyser <ptyser@xes-inc.com>

Signed-off-by: NPeter Tyser <ptyser@xes-inc.com>

Signed-off-by: NPeter Tyser <ptyser@xes-inc.com>

Signed-off-by: NPeter Tyser <ptyser@xes-inc.com>

PPC boards are the only users of the current FPGA code which is littered
with manual relocation fixups.  Now that proper relocation is supported
for PPC boards, remove FPGA manual relocation.
Signed-off-by: NPeter Tyser <ptyser@xes-inc.com>

Signed-off-by: NPeter Tyser <ptyser@xes-inc.com>

Signed-off-by: NPeter Tyser <ptyser@xes-inc.com>

Signed-off-by: NPeter Tyser <ptyser@xes-inc.com>

Signed-off-by: NPeter Tyser <ptyser@xes-inc.com>