- 06 9月, 2016 3 次提交
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由 Andre Przywara 提交于
Casting "int"s to pointers is only valid for 32-bit systems. Add the appropriate pointer type cast to avoid a compiler warning when compiling for AArch64. Signed-off-by: NAndre Przywara <andre.przywara@arm.com> Reviewed-by: NSiarhei Siamashka <siarhei.siamashka@gmail.com> Signed-off-by: NHans de Goede <hdegoede@redhat.com>
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由 Andre Przywara 提交于
There is no "CONFIG_MACH_SUN50I_A64" in upstream U-Boot, so fix the name to prevent the option to be enabled. Signed-off-by: NAndre Przywara <andre.przywara@arm.com> Reviewed-by: NHans de Goede <hdegoede@redhat.com> Signed-off-by: NHans de Goede <hdegoede@redhat.com>
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由 Andre Przywara 提交于
This commit moved the SPL stack into SRAM C, which worked when the SPL set the AHB1 clock down to 100 MHz to cope with the flaky SRAM C access from the CPU. However booting with boot0 (and thus not using SPL at all) we still run with a 200 MHz AHB1, so any access to SRAM C is prone to fail. Since this commit does _not_ only affect the SPL code, but also the U-Boot proper, we fail when booting with boot0. As the introduction of tiny-printf reduced the size of the SPL, we can afford to have the SPL stack in SRAM A1. This reverts commit 1a83fb4a and fixes booting the Pine64 when using boot0. Signed-off-by: NAndre Przywara <andre.przywara@arm.com> Reviewed-by: NSiarhei Siamashka <siarhei.siamashka@gmail.com> Signed-off-by: NHans de Goede <hdegoede@redhat.com>
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- 03 9月, 2016 7 次提交
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由 Hans de Goede 提交于
The Orange Pi Plus2E is an extended version of the Orange Pi Pc Plus, with 2G RAM and an external gbit ethernet phy. The dts file is identical to the one submitted to the upstream kernel, except that it has the pending patch to enable the ethernet controller squashed in, as u-boot already has sun8i-emac support. Signed-off-by: NHans de Goede <hdegoede@redhat.com>
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由 Hans de Goede 提交于
The Orange Pi 2 and Orange Pi Plus also come with ethernet, enable support for this. Signed-off-by: NHans de Goede <hdegoede@redhat.com>
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由 Hans de Goede 提交于
This adds an emac node to the orangepi-2 dts (not yet merged upstream, but in u-boot we already have emac support); fixes the alphetically sorting of nodes in sun8i-h3-orangepi-plus.dts and disables some usb controllers in sun8i-h3-orangepi-plus.dts which are only used on the plus2e, as upstream has decided to do a separate dts files for the plus2e. Signed-off-by: NHans de Goede <hdegoede@redhat.com>
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由 Chen-Yu Tsai 提交于
The sun8i-emac driver follows an old version of the proposed DT bindings, where the EMAC clock and EPHY control register range is listed directly, rather than through a syscon phandle. Add back the syscon register range to avoid an invalid data access. We should fix the driver once the Linux kernel bindings have been finalized. Signed-off-by: NChen-Yu Tsai <wens@csie.org> Reviewed-by: NHans de Goede <hdegoede@redhat.com> Signed-off-by: NHans de Goede <hdegoede@redhat.com>
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由 Stefan Mavrodiev 提交于
A33-OLinuXino is A33 development board designed by Olimex LTD. It has AXP223 PMU, 1GB DRAM, a micro SD card, one USB-OTG connector, headphone and mic jacks, connector for LiPo battery and optional 4GB NAND Flash. It has two 40-pin headers. One for LCD panel, and one for additional modules. Also there is CSI/DSI connector. The dts files are identical to the ones submitted to the upstream kernel. Signed-off-by: NStefan Mavrodiev <stefan.mavrodiev@gmail.com> Reviewed-by: NHans de Goede <hdegoede@redhat.com> Signed-off-by: NHans de Goede <hdegoede@redhat.com>
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由 Icenowy Zheng 提交于
The iNet D978 rev2 is a tablet board designed by iNet, which is intended to use on 10" tablets with a appearance like Apple iPad. It has A33 SoC, 1GB RAM, 8GB/16GB NAND, SDIO Wi-Fi, a MicroUSB port and a MicroSD slot. Signed-off-by: NIcenowy Zheng <icenowy@aosc.xyz> Reviewed-by: NHans de Goede <hdegoede@redhat.com> Signed-off-by: NHans de Goede <hdegoede@redhat.com>
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由 Icenowy Zheng 提交于
Add a proper dts for the iNet D978 rev2 based A33 tablets. Signed-off-by: NIcenowy Zheng <icenowy@aosc.xyz> Acked-by: NHans de Goede <hdegoede@redhat.com> Signed-off-by: NHans de Goede <hdegoede@redhat.com>
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- 02 9月, 2016 1 次提交
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由 Peter Chubb 提交于
The Colorado TK1 SOM is a small form factor board similar to the Jetson TK1. The main differences lie in the pinmux, and in that the PCIe controller is set to use in 4lanes+1lane, rather than 2+2. The pinmux header here was generated from a spreadsheet provided by Colorado Engineering using the tegra-pinmux scripts. The spreadsheet was converted from v09 to v11 by me. Signed-off-by: NPeter Chubb <peter.chubb@data61.csiro.au> Acked-by: NStephen Warren <swarren@nvidia.com> Signed-off-by: NTom Warren <twarren@nvidia.com>
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- 31 8月, 2016 1 次提交
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由 Stephen Warren 提交于
The board ID EEPROM and board ID stickers on p2771-0000 will use a numeric versioning scheme, with version numbers such as 000/100/200/300/400/500. Within NVIDIA, these versions are also known as A00/A01/A02/A03/A04/B00. However, that numbering scheme is not easily visible outside of NVIDIA, and so does not make much sense to use. Convert U-Boot to use the readily visible numeric scheme. Also, it turns out that the current A02 DT actually applies to board versions 000/100/200 (A00..A02). Consequently rename this to 000 not 200 so that all U-Boot builds are named after the first version of the HW they support. Signed-off-by: NStephen Warren <swarren@nvidia.com> Signed-off-by: NTom Warren <twarren@nvidia.com>
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- 30 8月, 2016 6 次提交
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由 Bin Meng 提交于
This introduces two board defconfig files for generating EFI 32-bit and 64-bit payloads, to run on QEMU x86 target. With these in place, hopefully buildman will catch any build error with EFI payload support on x86. Signed-off-by: NBin Meng <bmeng.cn@gmail.com> Reviewed-by: NSimon Glass <sjg@chromium.org>
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由 Bin Meng 提交于
There are lots of warnings when building EFI 64-bit payload. include/asm-generic/bitops/__fls.h:17:2: warning: left shift count >= width of type if (!(word & (~0ul << 32))) { ^ In fact, U-Boot itself as EFI payload is running in 32-bit mode. So BITS_PER_LONG needs to still be 32, but EFI status codes are 64-bit when booting from 64-bit EFI. Introduce EFI_BITS_PER_LONG to bridge those status codes with U-Boot's BITS_PER_LONG. Signed-off-by: NBin Meng <bmeng.cn@gmail.com> Reviewed-by: NSimon Glass <sjg@chromium.org>
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由 Bin Meng 提交于
Since commit 73c5c399 "Makefile: Drop unnecessary -dtb suffixes", EFI payload does not build anymore. This fixes the build. Signed-off-by: NBin Meng <bmeng.cn@gmail.com> Reviewed-by: NSimon Glass <sjg@chromium.org>
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由 Simon Glass 提交于
Add a debug() at this point to help figure out what is wrong. Signed-off-by: NSimon Glass <sjg@chromium.org> Reviewed-by: NBin Meng <bmeng.cn@gmail.com>
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由 Simon Glass 提交于
Generally the microcode is combined into a single block only (and removed from the device tree) when there are multiple blocks. But this is not a requirement. Adjust the ivybridge code to avoid assuming this. Signed-off-by: NSimon Glass <sjg@chromium.org> Reviewed-by: NBin Meng <bmeng.cn@gmail.com>
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由 Simon Glass 提交于
Add a debug() at this point to help figure out what is wrong. Signed-off-by: NSimon Glass <sjg@chromium.org> Reviewed-by: Heiko Schocher<hs@denx.de> Reviewed-by: NBin Meng <bmeng.cn@gmail.com>
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- 28 8月, 2016 13 次提交
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由 Masahiro Yamada 提交于
This will be useful, for example, to load firmware to DRAM and make it visible to other agents. Signed-off-by: NMasahiro Yamada <yamada.masahiro@socionext.com>
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由 Masahiro Yamada 提交于
This is very likely to be necessary for normal use cases. Set its default to 'y' for shorter defconfig files. Signed-off-by: NMasahiro Yamada <yamada.masahiro@socionext.com>
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由 Masahiro Yamada 提交于
The eMMC on sLD3 is assigned with dedicated pins (only multiplexed with GPIO), so it shouldn't hurt to enable eMMC on SPL all the time. Signed-off-by: NMasahiro Yamada <yamada.masahiro@socionext.com>
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由 Masahiro Yamada 提交于
Commit 76c52ce2 ("ARM: uniphier: increase CONFIG_SYS_MALLOC_F_LEN to bind all nodes") missed to increase this config for sLD3. This change is needed to add "u-boot,dm-pre-reloc" to some nodes; more devices are bound, more malloc memory is needed. Signed-off-by: NMasahiro Yamada <yamada.masahiro@socionext.com>
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由 Masahiro Yamada 提交于
The revision of the original support card (rev 3.5, rev 3.6) fits in the 8 bit width revision register. When it was extended in a weird way, it was versioned in the format of "3.6.x" (where it should have been "3.7", of course). What is worse, only the sub-level version "6.x" was recorded in the 8 bit width register, completely ignoring the compatibility of the revision register format. This patch saves madly-versioned support cards by assuming the major version "3" when the MSB 4 bit of the register is read as "6". With this, the support card revision that were displayed as "6.10" is now corrected to "3.6.10". Signed-off-by: NMasahiro Yamada <yamada.masahiro@socionext.com>
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由 Masahiro Yamada 提交于
This supports the system reset via PSCI for ARMv7 SoCs. Because the system reset is not supported on PSCI 0.1, let's define CONFIG_ARMV7_PSCI_1_0. (it is supported since PSCI 0.2, but there is no CONFIG to enable it in U-Boot for now.) Signed-off-by: NMasahiro Yamada <yamada.masahiro@socionext.com>
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由 Masahiro Yamada 提交于
With this, we can save unnecessary udelay(). Signed-off-by: NMasahiro Yamada <yamada.masahiro@socionext.com>
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由 Masahiro Yamada 提交于
With the CONFIG_DM_MMC_OPS migration, the .set_ios callback can return an integer now. Return an appropriate error value rather than sudden death by BUG(). Signed-off-by: NMasahiro Yamada <yamada.masahiro@socionext.com>
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由 Masahiro Yamada 提交于
No more reason to define this function above the ops structure. Move it near the caller. Also, change its return type to void because it never fails. Signed-off-by: NMasahiro Yamada <yamada.masahiro@socionext.com>
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由 Masahiro Yamada 提交于
Catch up with the DM migration. As struct dm_mmc_ops does not have .init callback, call the init function directly from the probe function. Signed-off-by: NMasahiro Yamada <yamada.masahiro@socionext.com>
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由 Masahiro Yamada 提交于
They are both only referenced in this file. Signed-off-by: NMasahiro Yamada <yamada.masahiro@socionext.com>
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- 27 8月, 2016 9 次提交
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由 Kever Yang 提交于
This patch add maintainer information for rk3399 evb. Signed-off-by: NKever Yang <kever.yang@rock-chips.com> Acked-by: NSimon Glass <sjg@chromium.org> Reviewed-by: NAndreas Färber <afaerber@suse.de>
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由 Tony Lindgren 提交于
If we do nand device 0 command in u-boot on a device that has NAND support enabled but no NAND chip, we can get data abort at least on omaps. Fix the issue by replacing the check with nand_info[dev] as suggested by Scott Wood. The check for name existed before because before the array-to-pointer conversion there was no way to directly test nand_info[dev] for emptiness. Signed-off-by: NTony Lindgren <tony@atomide.com>
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由 Masahiro Yamada 提交于
Most of them are my mistakes. Signed-off-by: NMasahiro Yamada <yamada.masahiro@socionext.com>
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由 Masahiro Yamada 提交于
This is needed to move CONFIG options for the recently-added xtfpga_defconfig. The tarball of the pre-built toolchain can be downloaded from: https://www.kernel.org/pub/tools/crosstool/files/bin/x86_64/4.9.0/Signed-off-by: NMasahiro Yamada <yamada.masahiro@socionext.com>
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由 Stefan Agner 提交于
The page table is maintained by the CPU, hence it is safe to always align cache flush to a whole cache line size. This allows to use mmu_page_table_flush for a single page table, e.g. when configure only small regions through mmu_set_region_dcache_behaviour. Signed-off-by: NStefan Agner <stefan.agner@toradex.com> Tested-by: NFabio Estevam <fabio.estevam@nxp.com> Reviewed-by: NSimon Glass <sjg@chromium.org> Reviewed-by: NHeiko Schocher <hs@denx.de>
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由 Stefan Agner 提交于
Add LPAE support for mmu_set_region_dcache_behaviour. The function is in use in some LPAE capable board such TI DRA7xx or NXP i.MX 7. Signed-off-by: NStefan Agner <stefan.agner@toradex.com>
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由 Tom Rini 提交于
Use a tab not 8 spaces. Signed-off-by: NTom Rini <trini@konsulko.com>
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由 Tom Rini 提交于
This series moves the CONFIG_SYS_CACHELINE_SIZE. First, in nearly all cases we are mirroring the values used by the Linux Kernel here. Also, so long as (and in this case, it is true) we implement flushes in hunks that are no larger than the smallest implementation (and given that we mirror the Linux Kernel, again we are fine) it is OK to align higher. The biggest changes here are that we always use 64 bytes for CPU_V7 even if for example the underlying core is only 32 bytes (this mirrors Linux). Second, we say ARM64 uses 64 bytes not 128 (as found in the Linux Kernel) as we do not need multi-platform support (to this degree) and only the Cavium ThunderX 88xx series has a use for such large alignment. Cc: Albert Aribaud <albert.u.boot@aribaud.net> Cc: Marek Vasut <marex@denx.de> Cc: Stefano Babic <sbabic@denx.de> Cc: Prafulla Wadaskar <prafulla@marvell.com> Cc: Luka Perkov <luka.perkov@sartura.hr> Cc: Stefan Roese <sr@denx.de> Cc: Nagendra T S <nagendra@mistralsolutions.com> Cc: Vaibhav Hiremath <hvaibhav@ti.com> Acked-by: NLokesh Vutla <lokeshvutla@ti.com> Cc: Steve Rae <steve.rae@raedomain.com> Cc: Igor Grinberg <grinberg@compulab.co.il> Cc: Nikita Kiryanov <nikita@compulab.co.il> Cc: Stefan Agner <stefan.agner@toradex.com> Acked-by: NHeiko Schocher <hs@denx.de> Cc: Mateusz Kulikowski <mateusz.kulikowski@gmail.com> Cc: Peter Griffin <peter.griffin@linaro.org> Acked-by: NPaul Kocialkowski <contact@paulk.fr> Cc: Anatolij Gustschin <agust@denx.de> Acked-by: N"Pali Rohár" <pali.rohar@gmail.com> Cc: Adam Ford <aford173@gmail.com> Cc: Steve Sakoman <sakoman@gmail.com> Cc: Grazvydas Ignotas <notasas@gmail.com> Cc: Nishanth Menon <nm@ti.com> Cc: Stephen Warren <swarren@wwwdotorg.org> Cc: Robert Baldyga <r.baldyga@samsung.com> Cc: Minkyu Kang <mk7.kang@samsung.com> Cc: Thomas Weber <weber@corscience.de> Cc: Masahiro Yamada <yamada.masahiro@socionext.com> Cc: David Feng <fenghua@phytium.com.cn> Cc: Alison Wang <b18965@freescale.com> Cc: Michal Simek <michal.simek@xilinx.com> Cc: Simon Glass <sjg@chromium.org> Cc: York Sun <york.sun@nxp.com> Cc: Shengzhou Liu <Shengzhou.Liu@nxp.com> Cc: Mingkai Hu <mingkai.hu@nxp.com> Cc: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> Cc: Aneesh Bansal <aneesh.bansal@freescale.com> Cc: Saksham Jain <saksham.jain@nxp.com> Cc: Qianyu Gong <qianyu.gong@nxp.com> Cc: Wang Dongsheng <dongsheng.wang@nxp.com> Cc: Alex Porosanu <alexandru.porosanu@freescale.com> Cc: Hongbo Zhang <hongbo.zhang@nxp.com> Cc: tang yuantian <Yuantian.Tang@freescale.com> Cc: Rajesh Bhagat <rajesh.bhagat@nxp.com> Cc: Josh Wu <josh.wu@atmel.com> Cc: Bo Shen <voice.shen@atmel.com> Cc: Viresh Kumar <viresh.kumar@linaro.org> Cc: Hannes Schmelzer <oe5hpm@oevsv.at> Cc: Thomas Chou <thomas@wytron.com.tw> Cc: Joe Hershberger <joe.hershberger@ni.com> Cc: Sam Protsenko <semen.protsenko@linaro.org> Cc: Bin Meng <bmeng.cn@gmail.com> Cc: Christophe Ricard <christophe-h.ricard@st.com> Cc: Anand Moon <linux.amoon@gmail.com> Cc: Beniamino Galvani <b.galvani@gmail.com> Cc: Carlo Caione <carlo@endlessm.com> Cc: huang lin <hl@rock-chips.com> Cc: Sjoerd Simons <sjoerd.simons@collabora.co.uk> Cc: Xu Ziyuan <xzy.xu@rock-chips.com> Cc: "jk.kernel@gmail.com" <jk.kernel@gmail.com> Cc: "Ariel D'Alessandro" <ariel@vanguardiasur.com.ar> Cc: Kever Yang <kever.yang@rock-chips.com> Cc: Samuel Egli <samuel.egli@siemens.com> Cc: Chin Liang See <clsee@altera.com> Cc: Dinh Nguyen <dinguyen@opensource.altera.com> Cc: Hans de Goede <hdegoede@redhat.com> Cc: Ian Campbell <ijc@hellion.org.uk> Cc: Siarhei Siamashka <siarhei.siamashka@gmail.com> Cc: Boris Brezillon <boris.brezillon@free-electrons.com> Cc: Andre Przywara <andre.przywara@arm.com> Cc: Bernhard Nortmann <bernhard.nortmann@web.de> Cc: Wolfgang Denk <wd@denx.de> Cc: Ben Whitten <ben.whitten@gmail.com> Cc: Tom Warren <twarren@nvidia.com> Cc: Alexander Graf <agraf@suse.de> Cc: Sekhar Nori <nsekhar@ti.com> Cc: Vitaly Andrianov <vitalya@ti.com> Cc: "Andrew F. Davis" <afd@ti.com> Cc: Murali Karicheri <m-karicheri2@ti.com> Cc: Carlos Hernandez <ceh@ti.com> Cc: Ladislav Michl <ladis@linux-mips.org> Cc: Ash Charles <ashcharles@gmail.com> Cc: Mugunthan V N <mugunthanvnm@ti.com> Cc: Daniel Allred <d-allred@ti.com> Cc: Gong Qianyu <Qianyu.Gong@freescale.com> Signed-off-by: NTom Rini <trini@konsulko.com> Acked-by: NMasahiro Yamada <yamada.masahiro@socionext.com> Acked-by: NChin Liang See <clsee@altera.com> Tested-by: NStephen Warren <swarren@nvidia.com> Acked-by: NPaul Kocialkowski <contact@paulk.fr>
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