Signed-off-by: NStefan Roese <sr@denx.de>

Also display enabled/disabled RAID 6 support for 440SP/440SPe PPC's.
Signed-off-by: NStefan Roese <sr@denx.de>

This patch fixes a problem with an incorrect setup for the refresh
timer of the 44x DDR controller in the file cpu/ppc4xx/sdram.c
Signed-off-by: NStefan Roese <sr@denx.de>

This code will optimize the DDR2 controller setup on a board specific
basis.

Note: This code doesn't work right now on the NAND booting image for the
Sequoia board, since it doesn't fit into the 4kBytes for the SPL image.
Signed-off-by: NStefan Roese <sr@denx.de>

Signed-off-by: NHeiko Schocher <hs@denx.de>

The soc node of the mpc52xx needs to be loaded with the IPB bus frequency,
not the XLB frequency.

This patch depends on the previous patches for MPC52xx device tree support
Signed-off-by: NGrant Likely <grant.likely@secretlab.ca>
Signed-off-by: NSylvain Munaut <tnt@246tNt.com>

This patch adds support for the Prodrive P3M750 (PPC750 & MV64460)
and the P3M7448 (MPC7448 & MV64460) PMC modules. Both modules are
quite similar and share the same board directory "prodrive/p3mx"
and the same config file "p3mx.h".
Signed-off-by: NStefan Roese <sr@denx.de>

Implement various code style fixes and similar changes.
Signed-off-by: NTimur Tabi <timur@freescale.com>

This patch adds the code and configuration necessary to boot with an
arch/powerpc Linux kernel.
Signed-off-by: NGrant Likely <grant.likely@gmail.com>
Acked-by: NJon Loeliger <jdl@freescale.com>

Signed-off-by: NStefan Roese <sr@denx.de>

Patch below corrects the setting of the zmiifer register, it was
overwritting the register rather than ORing the settings.
Signed-off-by: NNeil Wilson <NWilson@airspan.com>
Signed-off-by: NStefan Roese <sr@denx.de>

Signed-off-by: NStefan Roese <sr@denx.de>

Signed-off-by: NStefan Roese <sr@denx.de>

Signed-off-by: NStefan Roese <sr@denx.de>

Signed-off-by: NStefan Roese <sr@denx.de>

Fixed cpu/ppc4xx/start.S for 440EPx Errata: further corrects PPC440EPx
errata 1.12: 440_33 by moving patch up in code.
Signed-off-by: NJeff Mann <mannj@embeddedplanet.com>
Signed-off-by: NStefan Roese <sr@denx.de>

Update the 83xx tree to use I2C support in drivers/fsl_i2c.c.  Delete
cpu/mpc83xx/i2c.c, include/asm-ppc/i2c.h, and all references to those files.
Added multiple I2C bus support to fsl_i2c.c.
Signed-off-by: NTimur Tabi <timur@freescale.com>

Replace all instances of CFG_IMMRBAR with CFG_IMMR, so that the 83xx
tree matches the other 8xxx trees.
Signed-off-by: NTimur Tabi <timur@freescale.com>

The 834x rev1.x silicon has one CPU5 errata.

The issue is when the data cache locked with
HID0[DLOCK], the dcbz instruction looks like no-op inst.

The right behavior of the data cache is when the data cache
Locked with HID0[DLOCK], the dcbz instruction allocates
new tags in cache.

The 834x rev3.0 and later and 8360 have not this bug inside.

So, when 834x rev3.0/8360 are working with ECC, the dcbz
instruction will corrupt the stack in cache, the processor will
checkstop reset.

However, the 834x rev1.x can work with ECC with these code,
because the sillicon has this cache bug. The dcbz will not
corrupt the stack in cache.
Really, it is the fault code running on fault sillicon.

This patch fix the incorrect dcbz operation. Instead of
CPU FP writing to initialise the ECC.

CHANGELOG:
* Fix the incorrect dcbz operation instead of CPU FP
writing to initialise the ECC memory. Otherwise, it
will corrupt the stack in cache, The processor will checkstop
reset.
Signed-off-by: NDave Liu <daveliu@freescale.com>

Update 83xx OF code to update local-mac-address properties
for ethernet instead of the obsolete 'address' property.

This patch also adds an improved I2C set_speed(), which handles all clock
frequencies.
Signed-off-by: NTimur Tabi <timur@freescale.com>

this patch adds support for the QUICC Engine based UCC gigabit ethernet device.

Add support for the Freescale MPC8360EMDS board.
Includes DDR, DUART, Local Bus, PCI.

PREREQUISITE PATCHES:

* This patch can only be applied after the following patches have been applied:

  1) DNX#2006090742000024 "Add support for multiple I2C buses"
  2) DNX#2006090742000033 "Multi-bus I2C implementation of MPC834x"
  3) DNX#2006091242000041 "Additional MPC8349 support for multibus i2c"
  4) DNX#2006091242000078 "Add support for variable flash memory sizes on 83xx systems"
  5) DNX#2006091242000069 "Add support for Errata DDR6 on MPC 834x systems"

CHANGELOG:

* Add support for the Freescale MPC8349E-mITX reference design platform.
  The second TSEC (Vitesse 7385 switch) is not supported at this time.
Signed-off-by: NTimur Tabi <timur@freescale.com>

Hello,

Attached is a patch implementing multiple I2C buses on the MPC834x CPU
family and the MPC8349EMDS board in particular.
This patch requires Patch 1 (Add support for multiple I2C buses).
Testing was performed on a 533MHz board.

/*** Note: This patch replaces ticket DNX#2006083042000027 ***/
Signed-off-by: NBen Warren <bwarren@qstreams.com>

CHANGELOG:
        Implemented driver-level code to support two I2C buses on the
MPC834x CPU family and the MPC8349EMDS board.  Available I2C bus speeds
are 50kHz, 100kHz and 400kHz on each bus.

regards,
Ben

CHANGELOG:

* Errata DDR6, which affects all current MPC 834x processors, lists changes
  required to maintain compatibility with various types of DDR memory.  This
  patch implements those changes.
Signed-off-by: NTimur Tabi <timur@freescale.com>

CHANGELOG:

* On 83xx systems, use the CFG_FLASH_SIZE macro to program the LBC local access
   window registers, instead of using a hard-coded value of 8MB.
Signed-off-by: NTimur Tabi <timur@freescale.com>

Incorporated the common unified variable names and the changes in preparation
for releasing mpc8360 patches.
Signed-off-by: NDave Liu <daveliu@freescale.com>

Removed unused file resetvec.S for mpc83xx cpu
Signed-off-by: NTanya Jiang <tanya.jiang@freescale.com>

Signed-off-by: NLadislav Michl <ladis@linux-mips.org>
Signed-off-by: NStefan Roese <sr@denx.de>

Signed-off-by: NJon Loeliger <jdl@freescale.com>

Patch by Stefan Roese, 24 Oct 2006

Patch by Haavard Skinnemoen, 06 Sep 2006

This patch adds support for the AT32AP CPU family and the AT32AP7000
chip, which is the first chip implementing the AVR32 architecture.

The AT32AP CPU core is a high-performance implementation featuring a
7-stage pipeline, separate instruction- and data caches, and a MMU.
For more information, please see the "AVR32 AP Technical Reference":

http://www.atmel.com/dyn/resources/prod_documents/doc32001.pdf

In addition to this, the AT32AP7000 chip comes with a large set of
integrated peripherals, many of which are shared with the AT91 series
of ARM-based microcontrollers from Atmel. Full data sheet is
available here:

http://www.atmel.com/dyn/resources/prod_documents/doc32003.pdfSigned-off-by: NHaavard Skinnemoen <hskinnemoen@atmel.com>

Introduced COFIG_FSL_I2C to select the common FSL I2C driver.
And removed hard i2c path from a few u-boot.lds scipts too.
Minor whitespace cleanups along the way.
Signed-off-by: NJon Loeliger <jdl@freescale.com>