The GARDENA smart Gateway boards are equipped with an Atmel / Microchip
AT91SAM9G25 SoC and with 128 MiB of RAM and 256 MiB of NAND storage.
This patch adds support for this board including SPL support. Therefore
the AT91Boostrap is not needed on this platform any more.
Signed-off-by: NStefan Roese <sr@denx.de>
Cc: Heiko Schocher <hs@denx.de>
Cc: Andreas Bießmann <andreas@biessmann.org>
Cc: Eugen Hristev <eugen.hristev@microchip.com>
Reviewed-by: NHeiko Schocher <hs@denx.de>

This makes it possible to reference the watchdog DT node via "&watchdog"
from board dts files.
Signed-off-by: NStefan Roese <sr@denx.de>
Cc: Heiko Schocher <hs@denx.de>
Cc: Andreas Bießmann <andreas@biessmann.org>
Cc: Eugen Hristev <eugen.hristev@microchip.com>
Reviewed-by: NHeiko Schocher <hs@denx.de>

This patch adds _image_binary_end to the SPL linker script. This will be
used be the upcoming GARDENA AT91SAM based platform, which uses DT in
SPL and configures CONFIGURE_SPL_SEPARATE_BSS.
Signed-off-by: NStefan Roese <sr@denx.de>
Cc: Heiko Schocher <hs@denx.de>
Cc: Andreas Bießmann <andreas@biessmann.org>
Cc: Eugen Hristev <eugen.hristev@microchip.com>
Reviewed-by: NHeiko Schocher <hs@denx.de>

This patch enables and starts the watchdog on the AT91 platform if
configured. The WD timeout value is read in the AT91 WD device driver
from the DT, using the "timeout-sec" DT property. If not provided in
the DT, the default value of 2 seconds is used.
Signed-off-by: NStefan Roese <sr@denx.de>
Cc: Heiko Schocher <hs@denx.de>
Cc: Andreas Bießmann <andreas@biessmann.org>
Cc: Eugen Hristev <eugen.hristev@microchip.com>

This patch adds a call to spl_early_init() to board_init_f() which is
needed when CONFIG_SPL_OF_CONTROL is configured. This is necessary for
the early SPL setup including the DTB setup for later usage.

Please note that this call might also be needed for non SPL_OF_CONTROL
board, like the smartweb target. But smartweb fails to build with this
call because its binary grows too big. So I disabled it for these kind
of targets for now.
Signed-off-by: NStefan Roese <sr@denx.de>
Cc: Heiko Schocher <hs@denx.de>
Cc: Andreas Bießmann <andreas@biessmann.org>
Cc: Eugen Hristev <eugen.hristev@microchip.com>
Reviewed-by: NHeiko Schocher <hs@denx.de>
Tested on the taurus board:
Tested-by: NHeiko Schocher <hs@denx.de>

Make sure that lowlevel_init is not compiled when
CONFIG_SKIP_LOWLEVEL_INIT_ONLY is configured.
Signed-off-by: NStefan Roese <sr@denx.de>
Cc: Heiko Schocher <hs@denx.de>
Cc: Andreas Bießmann <andreas@biessmann.org>
Cc: Eugen Hristev <eugen.hristev@microchip.com>
Reviewed-by: NHeiko Schocher <hs@denx.de>
Tested on the taurus board:
Tested-by: NHeiko Schocher <hs@denx.de>

Migrate the following options to CONFIG_DM:
  CONFIG_DM_GPIO
  CONFIG_DM_MMC
  CONFIG_DM_ETH
  CONFIG_DM_SERIAL
  CONFIG_DM_USB
Signed-off-by: NIlko Iliev <iliev@ronetix.at>

When introducing the SAMA5D27 SoCs, the SAMA5D2 series got an additional
chip id. The check if the cpu is sama5d2 was changed from a preprocessor
definition (inlining a call to 'get_chip_id()') to a C function,
probably to not call get_chip_id twice?

That however broke a check in the macb ethernet driver. That driver is
more generic and also used for other platforms. I suppose this solution
was implemented to use it in 'gem_is_gigabit_capable()', without having
to stricly depend on the at91 platform:

	#ifndef cpu_is_sama5d2
	#define cpu_is_sama5d2() 0
	#endif

That only works as long as cpu_is_sama5d2 is a preprocessor definition.
(The same is still true for sama5d4 by the way.) So this is a straight
forward fix for the workaround.

The not working check on the SAMA5D2 CPU lead to an issue on a custom
board with a LAN8720A ethernet phy connected to the SoC:

	=> dhcp
	ethernet@f8008000: PHY present at 1
	ethernet@f8008000: Starting autonegotiation...
	ethernet@f8008000: Autonegotiation complete
	ethernet@f8008000: link up, 1000Mbps full-duplex (lpa: 0xffff)
	BOOTP broadcast 1
	BOOTP broadcast 2
	BOOTP broadcast 3
	BOOTP broadcast 4
	BOOTP broadcast 5
	BOOTP broadcast 6
	BOOTP broadcast 7
	BOOTP broadcast 8
	BOOTP broadcast 9
	BOOTP broadcast 10
	BOOTP broadcast 11
	BOOTP broadcast 12
	BOOTP broadcast 13
	BOOTP broadcast 14
	BOOTP broadcast 15
	BOOTP broadcast 16
	BOOTP broadcast 17

	Retry time exceeded; starting again

Notice the wrong reported link speed, although both SoC and phy only
support 100 MBit/s!

The real issue on reliably detecting the features of that cadence
ethernet mac IP block, is probably more complicated, though.

Fixes: 245cbc58 ("ARM: at91: Get the Chip ID of SAMA5D2 SiP")
Signed-off-by: NAlexander Dahl <ada@thorsis.com>

Enabling DM_MMC is forcing CONFIG_BLK=y so if any board which uses
SCSI must need to enable DM_SCSI otherwise SCSI reads on that particular
target making invalid reading to the disk drive.

Allwinner platform do support SCSI on A10, A20 and R40 SoC's out of
these only A10 have DM_SCSI enabled. So enabling DM_MMC on A20, R40
would eventually end-up with scsi disk read failures like [1]

So, enable DM_MMC in all places of respective SoC's instead of enabling
them globally to Allwinner platform.

Now, DM_MMC is enabled in Allwinner SoC's except A20 and R40.

[1] https://lists.denx.de/pipermail/u-boot/2019-April/364057.htmlReported-by: NPablo Sebastián Greco <pgreco@centosproject.org>
Signed-off-by: NJagan Teki <jagan@amarulasolutions.com>

PHY cannot be detected unless we wait about 150 ms.
Signed-off-by: NAndrejs Cainikovs <andrejs.cainikovs@netmodule.com>
Reviewed-by: NAnatolij Gustschin <agust@denx.de>
Reviewed-by: NStefano Babic <sbabic@denx.de>
Acked-by: NJoe Hershberger <joe.hershberger@ni.com>

This patch moves all instances of static "watchdog_dev" declarations to
the "data" section. This may be needed, as the BSS may not be cleared
in the early U-Boot phase, where watchdog_reset() is already beeing
called. This may result in incorrect pointer access, as the check to
"!watchdog_dev" in watchdog_reset() may not be true and the function
may continue to run.
Signed-off-by: NStefan Roese <sr@denx.de>
Cc: Heiko Schocher <hs@denx.de>
Cc: Tom Rini <trini@konsulko.com>
Cc: Michal Simek <michal.simek@xilinx.com>
Cc: "Marek Behún" <marek.behun@nic.cz>
Cc: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
Tested-by: Michal Simek <michal.simek@xilinx.com> (on zcu100)
Reviewed-by: NMichal Simek <michal.simek@xilinx.com>

It occurs since commit 27cb7300
("Ensure device tree DTS is compiled").

More details can refer to
89c2b5c0
ARM: fix arch/arm/dts/Makefile
Signed-off-by: NRick Chen <rick@andestech.com>
Cc: Greentime Hu <greentime@andestech.com>
Reviewed-by: NBin Meng <bmeng.cn@gmail.com>
Reviewed-by: NLukas Auer <lukas.auer@aisec.fraunhofer.de>

Signed-off-by: NRick Chen <rick@andestech.com>
Cc: Greentime Hu <greentime@andestech.com>
Reviewed-by: NBin Meng <bmeng.cn@gmail.com>
Reviewed-by: NLukas Auer <lukas.auer@aisec.fraunhofer.de>

Limit the cache configuration only can be supported in M mode.
It can not be manipulated in S mode.
Signed-off-by: NRick Chen <rick@andestech.com>
Cc: Greentime Hu <greentime@andestech.com>
Reviewed-by: NBin Meng <bmeng.cn@gmail.com>
Reviewed-by: NLukas Auer <lukas.auer@aisec.fraunhofer.de>

Add ax25 RISC-V platform-specific Kconfig options,
to include CPU and timer drivers. Also disable
ATCPIT100 SoC timer and replace by PLMT.
Signed-off-by: NRick Chen <rick@andestech.com>
Cc: Greentime Hu <greentime@andestech.com>
Reviewed-by: NBin Meng <bmeng.cn@gmail.com>
Reviewed-by: NLukas Auer <lukas.auer@aisec.fraunhofer.de>

The platform-Level Machine Timer (PLMT) block
holds memory-mapped mtime register associated
with timer tick.

This driver implements the riscv_get_time() which
is required by the generic RISC-V timer driver.
Signed-off-by: NRick Chen <rick@andestech.com>
Cc: Greentime Hu <greentime@andestech.com>
Reviewed-by: NBin Meng <bmeng.cn@gmail.com>
Reviewed-by: NLukas Auer <lukas.auer@aisec.fraunhofer.de>

The Platform-Level Interrupt Controller (PLIC)
block holds memory-mapped claim and pending registers
associated with software interrupt. It is required
for handling IPI.
Signed-off-by: NRick Chen <rick@andestech.com>
Cc: Greentime Hu <greentime@andestech.com>
Reviewed-by: NBin Meng <bmeng.cn@gmail.com>
Reviewed-by: NLukas Auer <lukas.auer@aisec.fraunhofer.de>

Print an error message and hang if smp_call_function() returns an error,
indicating that relocation of the secondary harts has failed.
Signed-off-by: NLukas Auer <lukas.auer@aisec.fraunhofer.de>
Reviewed-by: NBin Meng <bmeng.cn@gmail.com>
Tested-by: NBin Meng <bmeng.cn@gmail.com>
Reviewed-by: NAnup Patel <anup.patel@wdc.com>

RISC-V U-Boot expects the hart ID to be passed to it via register a0 by
the previous boot stage. Machine mode firmware such as BBL and OpenSBI
do this when starting their payload (U-Boot) in supervisor mode. If
U-Boot is running in machine mode, this task must be handled by the boot
ROM. Explicitly populate register a0 with the hart ID from the mhartid
CSR to avoid possible problems on RISC-V processors with a boot ROM that
does not handle this task.
Suggested-by: NRick Chen <rick@andestech.com>
Signed-off-by: NLukas Auer <lukas.auer@aisec.fraunhofer.de>
Reviewed-by: NAnup Patel <anup.patel@wdc.com>
Reviewed-by: NAtish Patra <atish.patra@wdc.com>
Reviewed-by: NBin Meng <bmeng.cn@gmail.com>
Tested-by: NBin Meng <bmeng.cn@gmail.com>
Reviewed-by: NRick Chen <rick@andestech.com>
Tested-by: NRick Chen <rick@andestech.com>

Signed-off-by: NLukas Auer <lukas.auer@aisec.fraunhofer.de>
Reviewed-by: NAnup Patel <anup.patel@wdc.com>
Reviewed-by: NBin Meng <bmeng.cn@gmail.com>
Tested-by: NBin Meng <bmeng.cn@gmail.com>

On RISC-V, all harts boot independently. To be able to run on a
multi-hart system, U-Boot must be extended with the functionality to
manage all harts in the system. All harts entering U-Boot are registered
in the available_harts mask stored in global data. A hart lottery system
as used in the Linux kernel selects the hart U-Boot runs on. All other
harts are halted. U-Boot can delegate functions to them using
smp_call_function().

Every hart has a valid pointer to the global data structure and a 8KiB
stack by default. The stack size is set with CONFIG_STACK_SIZE_SHIFT.
Signed-off-by: NLukas Auer <lukas.auer@aisec.fraunhofer.de>
Reviewed-by: NAnup Patel <anup.patel@wdc.com>
Reviewed-by: NBin Meng <bmeng.cn@gmail.com>
Tested-by: NBin Meng <bmeng.cn@gmail.com>

The hart ID passed by the previous boot stage is currently stored in
register s0. If we divert the control flow inside a function, which is
required as part of multi-hart support, the function epilog may not be
called, clobbering register s0. Save the hart ID in the unallocatable
register tp instead to protect the hart ID.
Signed-off-by: NLukas Auer <lukas.auer@aisec.fraunhofer.de>
Reviewed-by: NBin Meng <bmeng.cn@gmail.com>
Reviewed-by: NRick Chen <rick@andestech.com>
Reviewed-by: NAnup Patel <anup.patel@wdc.com>

Move the initialization of the caches and the debug UART until after
board_init_f_init_reserve. This is in preparation for SMP support, where
code prior to this point will be executed by all harts. This ensures
that initialization will only be performed once on the main hart running
U-Boot.
Signed-off-by: NLukas Auer <lukas.auer@aisec.fraunhofer.de>
Reviewed-by: NAnup Patel <anup.patel@wdc.com>
Reviewed-by: NBin Meng <bmeng.cn@gmail.com>

The supervisor binary interface (SBI) provides the necessary functions
to implement the platform IPI functions riscv_send_ipi() and
riscv_clear_ipi(). Use it to implement them.

This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs
running in supervisor mode. Support for machine mode is already
available for CPUs that include the SiFive CLINT.
Signed-off-by: NLukas Auer <lukas.auer@aisec.fraunhofer.de>
Reviewed-by: NAnup Patel <anup.patel@wdc.com>
Reviewed-by: NBin Meng <bmeng.cn@gmail.com>
Reviewed-by: NAtish Patra <atish.patra@wdc.com>
Tested-by: NBin Meng <bmeng.cn@gmail.com>

Import the supervisor binary interface (SBI) header file from Linux
(arch/riscv/include/asm/sbi.h). The last change to it was in commit
6d60b6ee0c97 ("RISC-V: Device, timer, IRQs, and the SBI").
Signed-off-by: NLukas Auer <lukas.auer@aisec.fraunhofer.de>
Reviewed-by: NAnup Patel <anup.patel@wdc.com>
Reviewed-by: NBin Meng <bmeng.cn@gmail.com>
Reviewed-by: NAtish Patra <atish.patra@wdc.com>

Harts on RISC-V boot independently, U-Boot is responsible for managing
them. Functions are called on other harts with smp_call_function(),
which sends inter-processor interrupts (IPIs) to all other available
harts. Available harts are those marked as available in the device tree
and present in the available_harts mask stored in global data. The
available_harts mask is used to register all harts that have entered
U-Boot. Functions are specified with their address and two function
arguments (argument 2 and 3). The first function argument is always the
hart ID of the hart calling the function. On the other harts, the IPI
interrupt handler handle_ipi() must be called on software interrupts to
handle the request and call the specified function.

Functions are stored in the ipi_data data structure. Every hart has its
own data structure in global data. While this is not required at the
moment (all harts are expected to boot Linux), this does allow future
expansion, where other harts may be used for monitoring or other tasks.
Signed-off-by: NLukas Auer <lukas.auer@aisec.fraunhofer.de>
Reviewed-by: NAnup Patel <anup.patel@wdc.com>
Reviewed-by: NBin Meng <bmeng.cn@gmail.com>
Tested-by: NBin Meng <bmeng.cn@gmail.com>

After the commit: "eth: dm: fec: Add gpio phy reset binding"
SHA1: efd0b791

The FEC ETH driver switched to PHY GPIO reset performed with data defined
in DTS.
For the HSC|DDC boards the GPIO reset signal is active low and hence the
wrong DTS description must be changed (otherwise the reset for ETH is not
properly setup).
Signed-off-by: NLukasz Majewski <lukma@denx.de>

Activate I2C7 on Alt to allow access to the PMIC.
Signed-off-by: NMarek Vasut <marek.vasut+renesas@gmail.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>

Due to a final resolution not coming up in time for 2019.04 and
following the consensus on the discussion, we'll keep this around
for 2019.04 after all.

This reverts commit 0d968ceb.

This converts the following to Kconfig:
  CONFIG_ENV_SPI_BUS
  CONFIG_ENV_SPI_CS
  CONFIG_ENV_SPI_MAX_HZ
  CONFIG_ENV_SPI_MODE

Most of time these value are not needed, CONFIG_SF_DEFAULT
with same value is used, so I introduced CONFIG_USE_ENV_SPI_*
to force the associated value for the environment.
Signed-off-by: NPatrick Delaunay <patrick.delaunay@st.com>

Replace CONFIG_ENV_SPI_BASE by the better CONFIG_SYS_SPI_BASE
(it is not the location for environment but the location for U-Boot)
and, as it is the only platform with use this define, remove
it from whitelist.
Signed-off-by: NPatrick Delaunay <patrick.delaunay@st.com>

An ADATA 16GB Industrial MLC card has so much capacitance on the Vcc
pin that the usual toggling of regulator to power the card off and on
is insufficient. When the card is calibrated into UHS SDR104 mode, it
will remain in that mode across the power cycle and subsequent attempt
to communicate with the card will fail.

The test with this card is to insert it into an SDHI slot and perform
"mmc dev 0 ; mmc dev 0", where the second "mmc dev 0" will fail.

Fix this problem by increasing the off-on delay from 0 to 20 mS.
Signed-off-by: NMarek Vasut <marek.vasut+renesas@gmail.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>

Since commit 27cb7300 ("Ensure device tree DTS is compiled"),
build succeeds irrespective of the correctness of Makefile.

In fact, you can compile any defconfig without adding any entry in
arch/*/dts/Makefile.

I am going to revert that commit, so device tree must be explicitly
listed in Makefile.
Signed-off-by: NMasahiro Yamada <yamada.masahiro@socionext.com>
Reviewed-by: NDaniel Schwierzeck <daniel.schwierzeck@gmail.com>

Since commit 27cb7300 ("Ensure device tree DTS is compiled"),
build succeeds irrespective of the correctness of Makefile.

I am going to revert that commit, so wrong code must be fixed.

CONFIG_MCR3000 is not defined anywhere. CONFIG_TARGET_MCR3000 is the
correct one.
Signed-off-by: NMasahiro Yamada <yamada.masahiro@socionext.com>

Since commit 27cb7300 ("Ensure device tree DTS is compiled"),
build succeeds irrespective of the correctness of Makefile.

In fact, you can compile any defconfig without adding any entry in
arch/*/dts/Makefile.

As a result, a lot of wrong code have been merged unnoticed.

I am going to revert that commit, and lots of hidden issues have
come to light:

[1] Typos

  armada-3720-uDPU.dts, sun8i-a83t-tbs-a711.dts

  use the extension ".dts" instead of ".dtb"

[2] DTB is associated to undefined CONFIG option

  For example, mx6sllevk_defconfig defines CONFIG_MX6SLL, but
  associates its device tree to CONFIG_MX6SL, which is undefined.

[3] Lots of entries are missing
Signed-off-by: NMasahiro Yamada <yamada.masahiro@socionext.com>
Reviewed-by: NChris Packham <judge.packham@gmail.com>
[trini: add imx6ul pico dtbs]
Signed-off-by: NTom Rini <trini@konsulko.com>

Commit 1416e2d2 ("armv8: make SPL exception vectors optional") had a
typo in it which effectively disabled exception handling in SPL code always.

Since nobody complained, I guess we may as well disable exception handling
in SPL always by default.

So fix the bug to make the config option effective, but disable exception
handling in SPL by default. This gets us to the same functionality as before
by default, but with much less code included in the binary.
Signed-off-by: NAlexander Graf <agraf@suse.de>
Reviewed-by: NMatthias Brugger <mbrugger@suse.com>
Reviewed-by: NAndre Przywara <andre.przywara@arm.com>

Push the Starting kernel print to the end just before the
dm_remove_devices call.
Signed-off-by: NKeerthy <j-keerthy@ti.com>
Reviewed-by: NSimon Glass <sjg@chromium.org>

Prior to commit 93b283d4 ("ARM: CPU: arm926ejs: Consolidate cache
routines to common file") the kirkwood boards didn't have and dcache
support. The network and usb drivers rely on this. Set
CONFIG_SYS_DCACHE_OFF in the Kirkwood specific config.h.
Reported-by: NLeigh Brown <leigh@solinno.co.uk>
Signed-off-by: NChris Packham <judge.packham@gmail.com>
Reviewed-by: NStefan Roese <sr@denx.de>
Signed-off-by: NStefan Roese <sr@denx.de>

When armada-385.dtsi was sync'd from Linux the name of the node
describing the pcie controller was changed from pcie-controller to pcie.
Some of the boards that include armada-385.dtsi were missed in the
update retaining the old name. This updates the affected boards.
Reported-by: NВлад Мао <vlaomao@gmail.com>
Signed-off-by: NChris Packham <judge.packham@gmail.com>
Signed-off-by: NStefan Roese <sr@denx.de>

The conversion to DM_SPI managed to break accessing the environment on
dreamplug. This is because the environment code relies on being to able
to select the SPI device based on the sequence number. Add an alias so
that the spi0 bus gets sequence number 0.
Reported-by: NLeigh Brown <leigh@solinno.co.uk>
Signed-off-by: NChris Packham <judge.packham@gmail.com>
Tested-by: NLeigh Brown <leigh@solinno.co.uk>
Signed-off-by: NStefan Roese <sr@denx.de>