- 08 4月, 2021 40 次提交
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由 Breno Lima 提交于
When booting in low power or dual boot modes the M4 binary is authenticated by the M4 ROM code. Add an option in hab_status command so users can retrieve M4 HAB failure and warning events. => hab_status m4 Secure boot disabled HAB Configuration: 0xf0, HAB State: 0x66 No HAB Events Found! Add command documentation in mx6_mx7_secure_boot.txt guide. As HAB M4 API cannot be called from A7 core the code is parsing the M4 HAB persistent memory region. The HAB persistent memory stores HAB events, public keys and others HAB related information. The HAB persistent memory region addresses and sizes can be found in AN12263 "HABv4 RVT Guidelines and Recommendations". Reviewed-by: NUtkarsh Gupta <utkarsh.gupta@nxp.com> Reviewed-by: NYe Li <ye.li@nxp.com> Signed-off-by: NBreno Lima <breno.lima@nxp.com> Signed-off-by: NPeng Fan <peng.fan@nxp.com>
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由 Breno Lima 提交于
The HABv4 implementation in ROM checks if HAB major version in IVT header is 4.x. The current implementation in hab.c code is only validating HAB v4.0 and HAB v4.1 and may be incompatible with newer HABv4 versions. Modify verify_ivt_header() function to align with HABv4 implementation in ROM code. Signed-off-by: NBreno Lima <breno.lima@nxp.com> Reviewed-by: NYe Li <ye.li@nxp.com> Signed-off-by: NPeng Fan <peng.fan@nxp.com>
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由 Utkarsh Gupta 提交于
Add ability for hab_status command to show All HAB events and not just HAB failure events Signed-off-by: NUtkarsh Gupta <utkarsh.gupta@nxp.com> Reviewed-by: NYe Li <ye.li@nxp.com> Signed-off-by: NPeng Fan <peng.fan@nxp.com>
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由 Breno Lima 提交于
Currently it's not possible to authenticate additional boot images in HAB open configuration. The hab.c code is checking if the SEC_CONFIG[1] fuse is programmed prior to calling the hab_authenticate_image() API function. Users cannot check if their additional boot images has been correctly signed prior to closing their device. Enable hab.c to authenticate additional boot images in open mode so HAB events can be retrieved through get_hab_status() function. Signed-off-by: NBreno Lima <breno.lima@nxp.com> Reviewed-by: NYe Li <ye.li@nxp.com> Signed-off-by: NPeng Fan <peng.fan@nxp.com>
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由 Ye Li 提交于
Modify to use hab_rvt_failsafe function for failsafe ROM API, not directly call its ROM address. This function will wrap the sip call for iMX8M platforms. Signed-off-by: NYe Li <ye.li@nxp.com> Signed-off-by: NPeng Fan <peng.fan@nxp.com>
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由 Utkarsh Gupta 提交于
Calling csf_is_valid() with an un-signed image may lead to data abort as the CSF pointer could be pointing to a garbage address when accessed in HAB_HDR_LEN(*(const struct hab_hdr *)(ulong)ivt_initial->csf). Authenticate image from DDR location 0x80800000... Check CSF for Write Data command before authenticating image data abort pc : [<fff5494c>] lr : [<fff54910>] reloc pc : [<8780294c>] lr : [<87802910>] sp : fdf45dc8 ip : 00000214 fp : 00000000 r10: fffb6170 r9 : fdf4fec0 r8 : 00722020 r7 : 80f20000 r6 : 80800000 r5 : 80800000 r4 : 00720000 r3 : 17a5aca3 r2 : 00000000 r1 : 80f2201f r0 : 00000019 Flags: NzcV IRQs off FIQs off Mode SVC_32 Resetting CPU ... resetting ... To avoid such errors during authentication process, validate IVT structure by calling validate_ivt function which checks the following values in an IVT: IVT_HEADER = 0x4X2000D1 ENTRY != 0x0 RES1 = 0x0 DCD = 0x0 /* Recommended */ SELF != 0x0 /* Absoulute address of IVT */ CSF != 0x0 RES2 = 0x0 This commit also checks if Image's start address is 4 byte aligned. commit "0088d127 MLK-14945 HAB: Check if IVT valid before authenticating image" removed as this patch addresses the issue. Signed-off-by: NUtkarsh Gupta <utkarsh.gupta@nxp.com> Signed-off-by: NYe Li <ye.li@nxp.com> Signed-off-by: NPeng Fan <peng.fan@nxp.com>
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由 Peng Fan 提交于
There are some changes to support ARM64 i.MX8M platform in this patches: 1. The hab_rvt base and function vectors are different as i.MX6/7 2. Need to bypass an workaround for i.MX6 to fix problem in MMU. 3. The x18 register needed save & restore before calling any HAB API. According to ARM procedure call spec, the x18 is caller saved when it is used as temporary register. So calling HAB API may scratch this register, and cause crash once accessing the gd pointer. On ARMv7, the r9 is callee saved when it is used as variable register. So no need to save & restore it. 4. Add SEC_CONFIG fuse for iMX8M When current EL is not EL3, the direct calling to HAB will fail because CAAM/SNVS can't initialize at non-secure mode. In this case, we use SIP call to run the HAB in ATF. Signed-off-by: NYe Li <ye.li@nxp.com> Signed-off-by: NPeng Fan <peng.fan@nxp.com>
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由 Ye Li 提交于
When loading kernel image, the image size is parsed from header, so it does not include the CSF and IVT. Add back the authenticate_image function to wrap the imx_hab_authenticate_image with calculating IVT offset and full image size. Signed-off-by: NYe Li <ye.li@nxp.com> Signed-off-by: NPeng Fan <peng.fan@nxp.com>
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由 Breno Lima 提交于
Prior instantiating RNG we have to ensure if the CAAM job rings are available. Avoid hardcoded job ring max size and use the definition at fsl_sec.h Signed-off-by: NBreno Lima <breno.lima@nxp.com> Reviewed-by: NYe Li <ye.li@nxp.com> Signed-off-by: NPeng Fan <peng.fan@nxp.com>
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由 Breno Lima 提交于
Prior calling sec_in32() we have to ensure CAAM clock is enabled, the function sec_in32() is reading CAAM registers and if CAAM clock is disabled the system will hang. Signed-off-by: NBreno Lima <breno.lima@nxp.com> Reviewed-by: NYe Li <ye.li@nxp.com> Signed-off-by: NPeng Fan <peng.fan@nxp.com>
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由 Breno Lima 提交于
The CAAM output ring size register offset is currently defined in fsl_sec.h as FSL_CAAM_ORSR_JRa_OFFSET, use this definition to avoid hardcoded value in i.MX common code. Signed-off-by: NBreno Lima <breno.lima@nxp.com> Reviewed-by: NYe Li <ye.li@nxp.com> Signed-off-by: NPeng Fan <peng.fan@nxp.com>
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由 Breno Lima 提交于
This code was originally developed by Raul Cardenas <raul.casas@nxp.com> and modified to be applied in U-Boot imx_v2017.03. More information about the initial submission can be seen in the link below: https://lists.denx.de/pipermail/u-boot/2016-February/245273.html i.MX7D has an a protection feature for Manufacturing process. This feature uses asymmetric encryption to sign and verify authenticated software handled between parties. This command enables the use of such feature. The private key is unique and generated once per device. And it is stored in secure memory and only accessible by CAAM. Therefore, the public key generation and signature functions are the only functions available for the user. The manufacturing-protection authentication process can be used to authenticate the chip to the OEM's server. Command usage: Print the public key for the device. - mfgprot pubk Generates Signature over given data. - mfgprot sign <data_address> <data_size> Signed-off-by: NRaul Ulises Cardenas <raul.casas@nxp.com> Signed-off-by: NBreno Lima <breno.lima@nxp.com> Reviewed-by: NFabio Estevam <fabio.estevam@nxp.com> Reviewed-by: NYe Li <ye.li@nxp.com> Signed-off-by: NPeng Fan <peng.fan@nxp.com>
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由 Peng Fan 提交于
Add regs used by CAAM Signed-off-by: NPeng Fan <peng.fan@nxp.com>
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由 Peng 提交于
Add imx8mn_evk_defconfig to be maintained Typo fix Signed-off-by: NPeng <peng.fan@nxp.com>
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由 Ye Li 提交于
Both i.MX8MQ B1 and B2 should use default LPDDR4 script, while B0 has another dedicated script. Signed-off-by: NYe Li <ye.li@nxp.com> Reviewed-by: NPeng Fan <peng.fan@nxp.com> Signed-off-by: NPeng Fan <peng.fan@nxp.com>
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由 Ye Li 提交于
i.MX8MQ B2 also has fixed value in OCOTP_READ_FUSE_DATA register, so it does not support "fuse sense" command like B1. Signed-off-by: NYe Li <ye.li@nxp.com> Reviewed-by: NPeng Fan <peng.fan@nxp.com> Signed-off-by: NPeng Fan <peng.fan@nxp.com>
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由 Ye Li 提交于
i.MX8MQ B2 is using same value in OCOTP_READ_FUSE_DATA like B1, so we have to check the ROM verision to distinguish the revision. As we have checked the B1 rev for sticky bits work around in secure boot. So it won't apply on B2. Signed-off-by: NYe Li <ye.li@nxp.com> Reviewed-by: NPeng Fan <peng.fan@nxp.com> Signed-off-by: NPeng Fan <peng.fan@nxp.com>
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由 Peng Fan 提交于
The value of Unique ID in uboot and kernel is different for iMX8MP: serial#=02e1444a0002aaff root@imx8mpevk:/sys/devices/soc0# cat soc_uid D699300002E1444A The reason is that Fuse Addresses of Unique ID of iMX8MP are 0x420 and 0x430. Reviewed-by: NYe Li <ye.li@nxp.com> Signed-off-by: NAlice Guo <alice.guo@nxp.com> Signed-off-by: NPeng Fan <peng.fan@nxp.com>
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由 Ye Li 提交于
Users reported LPDDR4 MR12 value is set to 0 during PHY training, not the value from FSP timing structure, which cause compliance test failed. The root cause is the CATrainOpt[0] is set to 1 in 2D FSP timing but not set in 1D. According to PHY training application node, to enable the feature both 1D and 2D need set this field to 1, otherwise the training result will be incorrect. The PHY training doc also recommends to set CATrainOpt[0] to 0 to use MR12 value from message block (FSP structure). So update the LPDDR4 scripts of all mscale to clear CATrainOpt[0]. Signed-off-by: NYe Li <ye.li@nxp.com> Reviewed-by: NJacky Bai <ping.bai@nxp.com> Signed-off-by: NPeng Fan <peng.fan@nxp.com>
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由 Peng Fan 提交于
Update fuse path to disable modules correctly. Reviewed-by: NYe Li <ye.li@nxp.com> Signed-off-by: NPeng Fan <peng.fan@nxp.com>
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由 Ye Li 提交于
For dual core and single core iMX8M parts, the thermal node and PMU node in kernel DTB also needs update to remove the refers to deleted core nodes. Otherwise both driver will fail to work. Signed-off-by: NYe Li <ye.li@nxp.com> Reviewed-by: NPeng Fan <peng.fan@nxp.com> Signed-off-by: NPeng Fan <peng.fan@nxp.com>
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由 Ye Li 提交于
There are 3 part numbers for 11x11 i.MX8MNano with different core number configuration: UltraLite Quad/Dual/Solo Comparing with i.MX8MN Lite parts, they have MIPI DSI disabled. So checking the MIPI DSI disable fuse to recognize these parts. Signed-off-by: NYe Li <ye.li@nxp.com> Reviewed-by: NPeng Fan <peng.fan@nxp.com> Signed-off-by: NPeng Fan <peng.fan@nxp.com>
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由 Ye Li 提交于
Add dedicated defconfigs for iMX8MN low drive mode which set the VDD_SOC and VDD_DRAM to 0.8v, DDR at 1600MTS (800Mhz clock) and GPU at 200Mhz. Signed-off-by: NYe Li <ye.li@nxp.com> Acked-by: NPeng Fan <peng.fan@nxp.com> Signed-off-by: NPeng Fan <peng.fan@nxp.com>
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由 Peng Fan 提交于
Add support for iMX8MN LPDDR4 EVK board which uses 2GB LPDDR4 and PCA9450B PMIC. Signed-off-by: NYe Li <ye.li@nxp.com> Signed-off-by: NPeng Fan <peng.fan@nxp.com>
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由 Peng Fan 提交于
uart clk has been enabled, no need enable again. Signed-off-by: NPeng Fan <peng.fan@nxp.com>
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由 Peng Fan 提交于
Currently PCA9450 might have address 0x25 or 0x35, so let user choose the address. Signed-off-by: NPeng Fan <peng.fan@nxp.com> Reviewed-by: NJaehoon Chung <jh80.chung@samsung.com>
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由 Jacky Bai 提交于
On i.MX8MN, we can only support DLL-ON mode only, so update the timing to support 2400mts & 1066mts setpoint. Signed-off-by: NJacky Bai <ping.bai@nxp.com> Reviewed-by: NYe Li <ye.li@nxp.com> Signed-off-by: NPeng Fan <peng.fan@nxp.com>
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由 Peng Fan 提交于
There is a frequency/timing limitation for SOC and ARM, if SOC is OD voltage/OD freq, then ARM can't run at ND voltage/1.2Ghz, it may have timing risk from SOC to ARM. Current VDD_SOC is set to 0.95v OD voltage in SPL, and kernel will increase bus clocks to OD frequency before it increases ARM voltage. So to conform to the limitation, we'd better increases VDD_ARM to OD voltage in SPL. Signed-off-by: NYe Li <ye.li@nxp.com> Signed-off-by: NPeng Fan <peng.fan@nxp.com>
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由 Peng Fan 提交于
Clean up the including headers Signed-off-by: NPeng Fan <peng.fan@nxp.com>
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由 haidong.zheng 提交于
VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: Nhaidong.zheng <haidong.zheng@nxp.com> Signed-off-by: NPeng Fan <peng.fan@nxp.com>
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由 Ye Li 提交于
Use more safer refresh time value for 6GB LPDDR4 on this EVK board. Update the parameters for every frequency point. Signed-off-by: NYe Li <ye.li@nxp.com> Reviewed-by: NJacky Bai <ping.bai@nxp.com> Signed-off-by: NPeng Fan <peng.fan@nxp.com>
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由 Ye Li 提交于
After switching to new LPDDR4 firmware 202006 version, have to update the LPDDR4 timing accordingly from RPA tool. Signed-off-by: NYe Li <ye.li@nxp.com> Tested-by: NSherry Sun <sherry.sun@nxp.com> Tested-by: NJacky Bai <ping.bai@nxp.com> Reviewed-by: NJacky Bai <ping.bai@nxp.com> Signed-off-by: NPeng Fan <peng.fan@nxp.com>
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由 Sherry Sun 提交于
Add inline ECC support for lpddr4 on imx8mp-evk. And add a config which can enable/disable inline ECC feature for lpddr4 on imx8mp-evk board. Signed-off-by: NSherry Sun <sherry.sun@nxp.com> Signed-off-by: NPeng Fan <peng.fan@nxp.com>
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由 Peng Fan 提交于
Add fdt_addr_r fdtfile which used by distro boot Clean up environment Signed-off-by: NPeng Fan <peng.fan@nxp.com>
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由 Peng Fan 提交于
Add fdt_addr_r fdtfile which used by distro boot Clean up environment Signed-off-by: NPeng Fan <peng.fan@nxp.com>
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由 Peng Fan 提交于
These files should not be in U-Boot repo Signed-off-by: NPeng Fan <peng.fan@nxp.com>
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由 Ye Li 提交于
Update PMIC to use PCA9540, the legacy board not supported by NXP Signed-off-by: NYe Li <ye.li@nxp.com>
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由 Ye Li 提交于
Update LPDDR4 script to sync with v2020.04 u-boot Signed-off-by: NYe Li <ye.li@nxp.com>
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由 Peng Fan 提交于
Fix the warning by set the variable zero to uint64_t "warning: ‘write’ reading 5 bytes from a region of size 4" Signed-off-by: NPeng Fan <peng.fan@nxp.com>
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由 Tom Rini 提交于
- Assorted Azure/GitLab improvements - Move the Dockerfile used for making containers in CI in to this repository.
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