- 02 6月, 2016 1 次提交
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由 Marek Vasut 提交于
Add support for board based on the popular Altera Cyclone V SoC. This board has the following properties: - 1 GiB of DRAM - 1 Gigabit ethernet - 1 USB gadget port - 1 USB host port with an on-board hub - 2 QSPI NORs connected to the Cadence QSPI core - Multiple I2C EEPROMs and one I2C temperature sensor Signed-off-by: NMarek Vasut <marex@denx.de> Cc: Dinh Nguyen <dinguyen@opensource.altera.com> Cc: Chin Liang See <clsee@altera.com> --- V2: Update the defconfig as per Tom's request
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- 10 4月, 2016 1 次提交
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由 Marek Vasut 提交于
The currently present DRAM timings generated from GHRD 14.0 did not work on SoCkit rev. D because they were too tight. Load the DRAM timings from GHRD 13.0 which are more relaxed and work with SoCkit rev. D. Signed-off-by: NMarek Vasut <marex@denx.de> Cc: Dinh Nguyen <dinguyen@opensource.altera.com> Cc: Chin Liang See <clsee@altera.com>
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- 04 9月, 2015 1 次提交
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由 Marek Vasut 提交于
Add support for Terasic SoCkit, which is CycloneV based board. The board can boot either from SD/MMC or QSPI. Ethernet is also supported. Signed-off-by: NMarek Vasut <marex@denx.de>
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- 23 8月, 2015 3 次提交
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由 Marek Vasut 提交于
Signed-off-by: NMarek Vasut <marex@denx.de>
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由 Marek Vasut 提交于
Just remove the CycloneV specific parts from the ArriaV SoCDK board and they are no longer needed now. Signed-off-by: NMarek Vasut <marex@denx.de>
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由 Marek Vasut 提交于
The board/altera/socfpga directory is not a generic SoCFPGA machine anymore, but instead it represents the Altera SoCDK board. To make matters more complicated, it represents both CycloneV and ArriaV variant. On the other hand, nowadays, the content of this board directory is mostly comprised of QTS-generated header files, while all the generic code is in arch/arm/mach-socfpga already. Thus, this patch splits the board/altera/socfpga into a separate board directory for ArriaV SoCDK and CycloneV SoCDK, so that each can be populated with the correct QTS-generated header files for that particular board. Signed-off-by: NMarek Vasut <marex@denx.de>
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- 08 8月, 2015 1 次提交
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由 Marek Vasut 提交于
Move all the files generated by Quartus into the qts/ subdir of the board/altera/socfpga dir to make them explicitly separate from the generic U-Boot code. Signed-off-by: NMarek Vasut <marex@denx.de> Cc: Dinh Nguyen <dinguyen@opensource.altera.com>
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- 05 3月, 2015 2 次提交
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由 Marek Vasut 提交于
Add support for the Altera Arria V development kit. Signed-off-by: NMarek Vasut <marex@denx.de> Cc: Chin Liang See <clsee@opensource.altera.com> Cc: Dinh Nguyen <dinguyen@opensource.altera.com> Cc: Pavel Machek <pavel@denx.de> Cc: Stefan Roese <sr@denx.de> Cc: Vince Bridgers <vbridger@opensource.altera.com>
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由 Marek Vasut 提交于
Replace multiple spaces with a single tab. Signed-off-by: NMarek Vasut <marex@denx.de> Cc: Chin Liang See <clsee@opensource.altera.com> Acked-by: NDinh Nguyen <dinguyen@opensource.altera.com> Acked-by: NPavel Machek <pavel@denx.de> Reviewed-by: NStefan Roese <sr@denx.de> Cc: Vince Bridgers <vbridger@opensource.altera.com>
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- 05 7月, 2014 1 次提交
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由 Chin Liang See 提交于
Scan Manager driver will be called to configure the IOCSR scan chain. This configuration will setup the IO buffer settings Signed-off-by: NChin Liang See <clsee@altera.com> Cc: Dinh Nguyen <dinguyen@altera.com> Cc: Wolfgang Denk <wd@denx.de> CC: Pavel Machek <pavel@denx.de> Cc: Tom Rini <trini@ti.com> Cc: Albert Aribaud <albert.u.boot@aribaud.net>
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