MPC837xE specs says that SerDes1 has:

— Two lanes running x1 SGMII at 1.25 Gbps;
— Two lanes running x1 SATA at 1.5 or 3.0 Gbps.

And for SerDes2:

— Two lanes running x1 PCI Express at 2.5 Gbps;
— One lane running x2 PCI Express at 2.5 Gbps;
— Two lanes running x1 SATA at 1.5 or 3.0 Gbps.

The spec also explicitly states that PEX options are not valid for
the SD1.

Nevertheless MPC8378 RDB and MDS boards configure the SD1 for PEX,
which is wrong to do.
Signed-off-by: NAnton Vorontsov <avorontsov@ru.mvista.com>
Signed-off-by: NKim Phillips <kim.phillips@freescale.com>

Currently 64M of LBC SDRAM are mapped at 0xF0000000 which makes
it difficult to use (b/c then the memory is discontinuous and
there is quite big memory hole between the DDR/SDRAM regions).

This patch reworks LBC SDRAM setup so that now we dynamically
place the LBC SDRAM near the DDR (or at 0x0 if there isn't any
DDR memory).

With this patch we're able to:

- Boot without external DDR memory;
- Use most "DDR + SDRAM" setups without need to support for
  sparse/discontinuous memory model in the software.
Signed-off-by: NAnton Vorontsov <avorontsov@ru.mvista.com>
Signed-off-by: NKim Phillips <kim.phillips@freescale.com>

On some systems (for example Fedora Core 4) U-Boot builds with the
following wanrings only:

...
In file included from /home/wd/git/u-boot/include/libfdt_env.h:33,
                 from fdt.c:51:
		 /usr/include/asm/byteorder.h:6:2: warning: #warning using private kernel header; include <endian.h> instead!

This patch fixes this problem.
Signed-off-by: NWolfgang Denk <wd@denx.de>

Signed-off-by: NStefan Roese <sr@denx.de>

Previously only the NOR flash mapping was written into the ranges
property of the ebc node. This patch now writes all enabled chip
select areas into the ranges property.
Signed-off-by: NStefan Roese <sr@denx.de>

Signed-off-by: NDirk Eibach <eibach@gdsys.de>
Signed-off-by: NStefan Roese <sr@denx.de>

I reorganized my config files, putting the common stuff into netstal-common.h
(got the idea by looking a amcc-common.h from Stefan).

Added stuff to boot the new powerpc linux via NFS (only tested with HCU4).
Signed-off-by: NNiklaus Giger <niklaus.giger@netstal.com>
Signed-off-by: NStefan Roese <sr@denx.de>

Provide a weak defined routine to retrieve the CPU number for
reference boards that have multiple CPU's.  Default behavior
is the existing single CPU print output.  Reference boards with
multiple CPU's need to provide a board specific routine.
See board/amcc/arches/arches.c for an example.
Signed-off-by: NAdam Graham <agraham@amcc.com>
Signed-off-by: NVictor Gallardo <vgallardo@amcc.com>
Signed-off-by: NStefan Roese <sr@denx.de>

This patch add the capability to configure a PPC440 based IBM SDRAM
Controller with static, compiled-in, values. PPC440 memory subsystem
includes a Memory Queue core.
Signed-off-by: NAdam Graham <agraham@amcc.com>
Signed-off-by: NVictor Gallardo <vgallardo@amcc.com>
Signed-off-by: NStefan Roese <sr@denx.de>

The Arches Evaluation board is based on the AMCC 460GT SoC chip.
This board is a dual processor board with each processor providing
independent resources for Rapid IO, Gigabit Ethernet, and serial
communications. Each 460GT has it's own 512MB DDR2 memory, 32MB NOR
FLASH, UART, EEPROM and temperature sensor, along with a shared debug
port. The two 460GT's will communicate with each other via shared
memory, Gigabit Ethernet and x1 PCI-Express.
Signed-off-by: NAdam Graham <agraham@amcc.com>
Signed-off-by: NVictor Gallardo <vgallardo@amcc.com>
Signed-off-by: NStefan Roese <sr@denx.de>

Several customers have reported problems with the environment in
EEPROM, including corrupted content after board reset. Probably the
code to prevent I2C Enge Conditions is not working sufficiently.

We move the environment to flash now, which allows to have a backup
copy plus gives much faster boot times.

Also, change the default console initialization to 115200 bps as used
on most other boards.
Signed-off-by: NWolfgang Denk <wd@denx.de>

mpc8536ds.c: In function 'is_sata_supported':
mpc8536ds.c:615: warning: unused variable 'devdisr'
Signed-off-by: NKumar Gala <galak@kernel.crashing.org>

Signed-off-by: NWolfgang Denk <wd@denx.de>

Signed-off-by: NWolfgang Denk <wd@denx.de>

Round clock frequencies for printing.

Many boards printed off clock frequencies like 399 MHz instead of the
exact 400 MHz because numberes were not rounded. This is fixed now.
Signed-off-by: NWolfgang Denk <wd@denx.de>

Commit f7d190b1 corrected the value of MPC85xx_PORDEVSR2_SEC_CFG, but forgot
to add a comment that the correct value disagrees with the 8544 reference
manual.  The changelog for that commit is also wrong, as it says "bit 28"
when it should be "bit 24".
Signed-off-by: NTimur Tabi <timur@freescale.com>

Conflicts:

	drivers/usb/usb_ohci.c

Conflicts:

	board/freescale/mpc8536ds/mpc8536ds.c
	include/configs/mgcoge.h
Signed-off-by: NWolfgang Denk <wd@denx.de>

Signed-off-by: NHeiko Schocher <hs@denx.de>

Signed-off-by: NHeiko Schocher <hs@denx.de>

Signed-off-by: NJason Jin <Jason.jin@freescale.com>

This patch based on Andy's work.
Including command 'pixis_set_sgmii' support.
Signed-off-by: NLiu Yu <yu.liu@freescale.com>

The pixis sgmii command depend on the FPGA support on the board, some 85xx
boards support SGMII riser card but did not support this command, define
CONFIG_PIXIS_SGMII_CMD for those boards which support the sgmii command.

Not like 8544, 8572 has 4 eTsec so that the other two's pixis bits
are not supported by 8544. Therefor, define PIXIS_VSPEED2_MASK and
PIXIS_VCFGEN1_MASK in header file for both boards.
Signed-off-by: NLiu Yu <yu.liu@freescale.com>

Signed-off-by: NEd Swarthout <Ed.Swarthout@freescale.com>

Debug sessions may have left enabled laws.
Changing lawbar with an unkown enabled tgtid could cause problems.
Signed-off-by: NEd Swarthout <Ed.Swarthout@freescale.com>

mpc8572 supports all pcie controllers as end-points with cfg_host_agent=0.
Include host_agent == 0 decode for end-point determination.

This is not needed for the ds reference board since pcie3 will be a host
in order to connect to the uli chip.  Include it here as a reference for
other mpc8572 boards.
Signed-off-by: NEd Swarthout <Ed.Swarthout@freescale.com>

Signed-off-by: NEd Swarthout <Ed.Swarthout@freescale.com>

Signed-off-by: NEd Swarthout <Ed.Swarthout@freescale.com>

Some cores don't support ethernet stashing at all, and some
instances have errata.  Adds 3 properties to gianfar nodes
which support stashing.  For now, just add this support to
85xx SoCs.
Signed-off-by: NAndy Fleming <afleming@freescale.com>

* Add board specific parameter table to choose correct cpo, clk_adjust,
write_data_delay based on board ddr frequency and n_ranks.

* Set odt_rd_cfg and odt_wr_cfg based on the dimm# and CS#.
Signed-off-by: NJames Yang <James.Yang@freescale.com>
Signed-off-by: NHaiying Wang <Haiying.Wang@freescale.com>

* Add board specific parameter table to choose correct cpo, clk_adjust,
write_data_delay, 2T based on board ddr frequency and n_ranks.

* Set odt_rd_cfg and odt_wr_cfg based on the dimm# and CS#.

* Set memory controller interleaving mode to bank interleaving, and disable
bank(chip select) interleaving mode by default, because the default on-board
DDR DIMMs are 2x512MB single-rank.

* Change CONFIG_ICS307_REFCLK_HZ from 33333333 to 33333000.
Signed-off-by: NJames Yang <James.Yang@freescale.com>
Signed-off-by: NHaiying Wang <Haiying.Wang@freescale.com>

Signed-off-by: NHaiying Wang <Haiying.Wang@freescale.com>

* Check DDR interleaving mode from environment by reading memctl_intlv_ctl and
ba_intlv_ctl.
* Print DDR interleaving mode information
* Add doc/README.fsl-ddr to describe the interleaving setting
Signed-off-by: NHaiying Wang <Haiying.Wang@freescale.com>

Because some dimm parameters like n_ranks needs to be used with the board
frequency to choose the board parameters like clk_adjust etc. in the
board_specific_paramesters table of the board ddr file, we need to pass
the dimm parameters to the board file.

* move ddr dimm parameters header file from /cpu to /include directory.
* add ddr dimm parameters to populate board specific options.
* Fix fsl_ddr_board_options() for all the 8xxx boards which call this function.
Signed-off-by: NHaiying Wang <Haiying.Wang@freescale.com>

Fix some bugs:
  1. Correctly set intlv_ctl in cs_config.
  2. Correctly set sa, ea in cs_bnds when bank interleaving mode is enabled.
  3. Set base_address and total memory for each ddr controller in memory
     controller interleaving mode.
Signed-off-by: NHaiying Wang <Haiying.Wang@freescale.com>

Signed-off-by: NKumar Gala <galak@kernel.crashing.org>

Changing the flash from cacheable to cache-inhibited was taking a significant
amount of time due to the fact that we were iterating over the full 256M of
flash.  Instead we can just flush the L1 d-cache and invalidate the i-cache.
Signed-off-by: NKumar Gala <galak@kernel.crashing.org>

Added the ability for C code to invalidate the i/d-cache's and
to flush the d-cache.  This allows us to more efficient change mappings
from cache-able to cache-inhibited.
Signed-off-by: NKumar Gala <galak@kernel.crashing.org>