- 12 5月, 2021 22 次提交
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由 Dave Gerlach 提交于
Add initial A53 defconfig support for AM64x SoCs. Signed-off-by: NDave Gerlach <d-gerlach@ti.com>
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由 Dave Gerlach 提交于
Add initial R5 defconfig support for AM64x SoCs. Signed-off-by: NDave Gerlach <d-gerlach@ti.com>
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由 Dave Gerlach 提交于
Add initial support for dt that runs on r5. Signed-off-by: NDave Gerlach <d-gerlach@ti.com>
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由 Dave Gerlach 提交于
The AM642 EValuation Module (EVM) is a board that provides access to various peripherals available on the AM642 SoC, such as PCIe, USB 2.0, CPSW Ethernet, ADC, and more. Add basic support. Signed-off-by: NDave Gerlach <d-gerlach@ti.com>
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由 Dave Gerlach 提交于
The AM642 SoC belongs to the K3 Multicore SoC architecture platform, providing advanced system integration to enable applications such as Motor Drives, PLC, Remote IO and IoT Gateways. Some highlights of this SoC are: * Dual Cortex-A53s in a single cluster, two clusters of dual Cortex-R5F MCUs, and a single Cortex-M4F. * Two Gigabit Industrial Communication Subsystems (ICSSG). * Integrated Ethernet switch supporting up to a total of two external ports. * PCIe-GEN2x1L, USB3/USB2, 2xCAN-FD, eMMC and SD, UFS, OSPI memory controller, QSPI, I2C, eCAP/eQEP, ePWM, ADC, among other peripherals. * Centralized System Controller for Security, Power, and Resource Management (DMSC). See AM64X Technical Reference Manual (SPRUIM2, Nov 2020) for further details: https://www.ti.com/lit/pdf/spruim2 Introduce basic support for the AM642 SoC to enable SD/MMC boot. Introduce a limited set of MAIN domain peripherals under cbass_main and a set of MCU domain peripherals under cbass_mcu. Signed-off-by: NDave Gerlach <d-gerlach@ti.com>
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由 Dave Gerlach 提交于
Add pinctrl macros for AM64 SoC. These macro definitions are similar to that of previous platforms, but adding new definitions to avoid any naming confusions in the soc dts files. Signed-off-by: NDave Gerlach <d-gerlach@ti.com>
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由 Dave Gerlach 提交于
Add board specific initialization for am64x based boards. Signed-off-by: NDave Gerlach <d-gerlach@ti.com>
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由 Dave Gerlach 提交于
AM64x uses a different thread mapping that existing K3 SoCs, so update the valid thread ID list to include those used for AM64x. Also remove the comment identifying the purpose of each thread ID. The purpose of the thread ID is specified when describing the threads in the device tree and the same ID can mean different things on different SoCs, so the comment is not useful. Signed-off-by: NDave Gerlach <d-gerlach@ti.com>
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由 Dave Gerlach 提交于
Add support for the controller present on the AM642 SoC. There are instances: sdhci0: 8bit bus width, max 400 MBps sdhci1: 4bit bus width, max 100 MBps Signed-off-by: NDave Gerlach <d-gerlach@ti.com>
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由 Keerthy 提交于
Change the memory attributes for the DDR regions used by the remote processors on AM65x so that the cores can see and execute the proper code. A separate table based on the previous K3 SoCs is introduced since the number of remote processors and their DDR usage is different between the SoC families. Signed-off-by: NKeerthy <j-keerthy@ti.com> Signed-off-by: NDave Gerlach <d-gerlach@ti.com>
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由 Suman Anna 提交于
The AM642 SoCs use the Main R5FSS0 as a boot processor, and runs the R5 SPL that performs the initialization of the System Controller processor and starting the Arm Trusted Firmware (ATF) on the Arm Cortex A53 cluster. The Core0 serves as this boot processor and is parked in WFE after all the initialization. Core1 does not directly participate in the boot flow, and is simply parked in a WFI. Power down these R5 cores (and the associated RTI timer resources that were indirectly powered up) after starting up ATF on A53 by using the appropriate SYSFW API in release_resources_for_core_shutdown(). This allows these Main R5F cores to be further controlled from the A53 to run regular applications. Signed-off-by: NSuman Anna <s-anna@ti.com> Signed-off-by: NDave Gerlach <d-gerlach@ti.com>
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由 Dave Gerlach 提交于
To avoid any glitches on MMC clock line, make use of pm per and post callbacks when loading sysfw. Signed-off-by: NDave Gerlach <d-gerlach@ti.com>
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由 Dave Gerlach 提交于
Use the System Firmware (SYSFW) loader framework to load and start the SYSFW as part of the AM642 early initialization sequence. Also make use of existing logic to detect if ROM has already loaded sysfw and avoided attempting to reload and instead just prepare to use already running firmware. While at it also initialize the MAIN_UART1 pinmux as it is used by SYSFW to print diagnostic messages. Signed-off-by: NDave Gerlach <d-gerlach@ti.com>
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由 Dave Gerlach 提交于
For AM642, ROM supports loading system firmware directly from boot image. ROM passes information about the number of images that are loaded to bootloader at a specific address that is temporary. Add support for storing this information somewhere permanent before it gets corrupted. Signed-off-by: NDave Gerlach <d-gerlach@ti.com>
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由 Dave Gerlach 提交于
To access various control MMR functionality the registers need to be unlocked. Do that for all control MMR regions in the MAIN domain. Signed-off-by: NDave Gerlach <d-gerlach@ti.com>
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由 Keerthy 提交于
AM642 allows for booting from primary or backup boot media. Both media can be chosen individually based on switch settings. ROM looks for a valid image in primary boot media, if not found then looks in backup boot media. In order to pass this boot media information to boot loader, ROM stores a value at a particular address. Add support for reading this information and determining the boot media correctly. Signed-off-by: NKeerthy <j-keerthy@ti.com> Signed-off-by: NDave Gerlach <d-gerlach@ti.com>
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由 Dave Gerlach 提交于
The AM642 SoC belongs to the K3 Multicore SoC architecture platform, providing advanced system integration to enable applications such as Motor Drives, PLC, Remote IO and IoT Gateways. Some highlights of this SoC are: * Dual Cortex-A53s in a single cluster, two clusters of dual Cortex-R5F MCUs, and a single Cortex-M4F. * Two Gigabit Industrial Communication Subsystems (ICSSG). * Integrated Ethernet switch supporting up to a total of two external ports. * PCIe-GEN2x1L, USB3/USB2, 2xCAN-FD, eMMC and SD, UFS, OSPI memory controller, QSPI, I2C, eCAP/eQEP, ePWM, ADC, among other peripherals. * Centralized System Controller for Security, Power, and Resource Management (DMSC). See AM64X Technical Reference Manual (SPRUIM2, Nov 2020) for further details: https://www.ti.com/lit/pdf/spruim2Signed-off-by: NDave Gerlach <d-gerlach@ti.com>
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由 Dario Binacchi 提交于
This reverts commit d64b9cdc. As pointed by [1] and [2], the reverted patch made every DT 'reg' property translatable. What the patch was trying to fix was fixed in a different way from previously submitted patches which instead of correcting the generic address translation function fixed the issue with appropriate platform code. [1] https://patchwork.ozlabs.org/project/uboot/patch/1614324949-61314-1-git-send-email-bmeng.cn@gmail.com/ [2] https://lore.kernel.org/linux-clk/20210402192054.7934-1-dariobin@libero.it/T/Signed-off-by: NDario Binacchi <dariobin@libero.it> Reviewed-by: NBin Meng <bmeng.cn@gmail.com>
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由 Dario Binacchi 提交于
Using the custom TI functions required not only replacing common memory access functions but also rewriting the routines used to set bypass and lock states. As for readl() and writel(), they also required the address of the register to be accessed, a parameter that is hidden by the TI clk module. Signed-off-by: NDario Binacchi <dariobin@libero.it>
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由 Dario Binacchi 提交于
Replaces the common memory access functions used by the driver with the ones exported from the TI clk module. Signed-off-by: NDario Binacchi <dariobin@libero.it>
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由 Dario Binacchi 提交于
The clock access functions exported by the clk header use the struct clk_ti_reg parameter to get the address of the register. This must also apply to clk_ti_latch(). Changes to TI's clk-mux and clk-divider drivers prevented the patch from generating compile errors. Signed-off-by: NDario Binacchi <dariobin@libero.it>
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由 Dario Binacchi 提交于
As pointed by [1] and [2], commit d64b9cdc ("fdt: translate address if #size-cells = <0>") is wrong: - It makes every 'reg' DT property translatable. It changes the address translation so that for an I2C 'reg' address you'll get back as reg the I2C controller address + reg value. - The quirk must be fixed with platform code. The clk_ti_get_reg_addr() is the platform code able to make the correct address translation for the AM33xx clocks registers. Its implementation was inspired by the Linux Kernel code. [1] https://patchwork.ozlabs.org/project/uboot/patch/1614324949-61314-1-git-send-email-bmeng.cn@gmail.com/ [2] https://lore.kernel.org/linux-clk/20210402192054.7934-1-dariobin@libero.it/T/Signed-off-by: NDario Binacchi <dariobin@libero.it>
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- 11 5月, 2021 1 次提交
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由 Tom Rini 提交于
Signed-off-by: NTom Rini <trini@konsulko.com>
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- 10 5月, 2021 4 次提交
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https://source.denx.de/u-boot/custodians/u-boot-x86由 Tom Rini 提交于
- x86: correct regwidth prompt in cbsysinfo - virtio: convert README.virtio to reST
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由 Bin Meng 提交于
This was missed when VirtIO support was initially brought to U-Boot back in 2018. Add an entry for it and list myself as the maintainer. Signed-off-by: NBin Meng <bmeng.cn@gmail.com>
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由 Bin Meng 提交于
This converts the existing README.virtio to reST, and puts it under the develop/driver-model/ directory. Signed-off-by: NBin Meng <bmeng.cn@gmail.com>
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由 Simon Glass 提交于
This should be 'regwidth', not 'baud'. Fix it. Signed-off-by: NSimon Glass <sjg@chromium.org> Reviewed-by: NBin Meng <bmeng.cn@gmail.com>
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- 07 5月, 2021 1 次提交
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- 06 5月, 2021 1 次提交
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由 Tom Rini 提交于
- Allow for boards to update bootargs before booting the OS (helpful in some forms of secure boot). - Enhance GPT write support. - gpio-sysinfo updates - Allow env to be appended from dtb
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- 05 5月, 2021 7 次提交
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由 Heinrich Schuchardt 提交于
The ebreak instruction should generate a breakpoint exception. Signed-off-by: NHeinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: NBin Meng <bmeng.cn@gmail.com> Reviewed-by: NRick Chen <rick@andestech.com>
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由 Dylan Jhong 提交于
Adding timeout mechanism to avoid spi driver from stucking in the while loop in __atcspi200_spi_xfer(). Signed-off-by: NDylan Jhong <dylan@andestech.com> Reviewed-by: NLeo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: NRick Chen <rick@andestech.com>
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由 Green Wan 提交于
Clear feature disable CSR to turn on all features of hart. The detail is specified at section, 'SiFive Feature Disable CSR', in user manual https://sifive.cdn.prismic.io/sifive/aee0dd4c-d156-496e-a6c4-db0cf54bbe68_sifive_U74MC_rtl_full_20G1.03.00_manual.pdfSigned-off-by: NGreen Wan <green.wan@sifive.com> Reviewed-by: NSean Anderson <seanga2@gmail.com> Reviewed-by: NBin Meng <bmeng.cn@gmail.com> Reviewed-by: NRick Chen <rick@andestech.com>
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由 Green Wan 提交于
Add a callback harts_early_init() to start.S to allow different riscv hart perform setup code for each hart as early as possible. Since all the harts enter the callback, they must be able to run the same setup. Signed-off-by: NGreen Wan <green.wan@sifive.com> Reviewed-by: NRick Chen <rick@andestech.com> Reviewed-by: NBin Meng <bmeng.cn@gmail.com>
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由 Niko Mauno 提交于
By declaring board-specific board_fdt_chosen_bootargs() the kernel command line arguments can be adjusted before injecting to flat dt chosen node. Signed-off-by: NNiko Mauno <niko.mauno@vaisala.com>
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由 Farhan Ali 提交于
This change would enhance the existing 'gpt read' command to allow (optionally) writing of the read GPT partitions to an environment variable in the UBOOT partitions layout format. This would allow users to easily change the overall partition settings by editing said variable and then using the variable in the 'gpt write' and 'gpt verify' commands. Signed-off-by: NFarhan Ali <farhan.ali@broadcom.com> Cc: Simon Glass <sjg@chromium.org> Cc: Heinrich Schuchardt <xypron.glpk@gmx.de> Cc: Corneliu Doban <cdoban@broadcom.com> Cc: Rayagonda Kokatanur <rayagonda.kokatanur@broadcom.com> Cc: Rasmus Villemoes <rasmus.villemoes@prevas.dk> Reviewed-by: NSimon Glass <sjg@chromium.org>
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由 Rasmus Villemoes 提交于
Check that a variable defined in /config/environment is found in the run-time environment, and that clearing fdt_env_path from within that node works. Reviewed-by: NSimon Glass <sjg@chromium.org> Signed-off-by: NRasmus Villemoes <rasmus.villemoes@prevas.dk> Acked-by: NJoe Hershberger <joe.hershberger@ni.com> [trini: Conditionalize the test being linked in] Signed-off-by: NTom Rini <trini@konsulko.com>
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- 04 5月, 2021 4 次提交
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由 Rasmus Villemoes 提交于
It can be useful to use the same U-Boot binary for multiple purposes, say the normal one, one for developers that allow breaking into the U-Boot shell, and one for use during bootstrapping which runs a special-purpose bootcmd. Or one can have several board variants that can share almost all boot logic, but just needs a few tweaks in the variables used by the boot script. To that end, allow the control dtb to contain a /config/enviroment node (or whatever one puts in fdt_env_path variable), whose property/value pairs are used to update the run-time environment after it has been loaded from its persistent location. The indirection via fdt_env_path is for maximum flexibility - for example, should the user wish (or board logic dictate) that the values in the DTB should no longer be applied, one simply needs to delete the fdt_env_path variable; that can even be done automatically by including a fdt_env_path = ""; property in the DTB node. Reviewed-by: NSimon Glass <sjg@chromium.org> Signed-off-by: NRasmus Villemoes <rasmus.villemoes@prevas.dk> Acked-by: NJoe Hershberger <joe.hershberger@ni.com>
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由 Sean Anderson 提交于
This adds a test for the gpio-sysinfo driver. Signed-off-by: NSean Anderson <sean.anderson@seco.com> Reviewed-by: NSimon Glass <sjg@chromium.org>
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由 Sean Anderson 提交于
This uses the newly-added dm_gpio_get_values_as_int_base3 function to implement a sysinfo device. The revision map is stored in the device tree. Signed-off-by: NSean Anderson <sean.anderson@seco.com> Reviewed-by: NSimon Glass <sjg@chromium.org>
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由 Sean Anderson 提交于
This has the uclass enforce calling detect() before other methods. This allows drivers to cache information in detect() and perform (cheaper) retrieval in the other accessors. This also modifies the only instance where this sequencing was not followed. Signed-off-by: NSean Anderson <sean.anderson@seco.com> Reviewed-by: NSimon Glass <sjg@chromium.org>
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