- 12 7月, 2017 1 次提交
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由 Stefano Babic 提交于
Change is consistent with other SOCs and it is in preparation for adding SOMs. SOC's related files are moved from cpu/ to mach-imx/<SOC>. This change is also coherent with the structure in kernel. Signed-off-by: NStefano Babic <sbabic@denx.de> CC: Fabio Estevam <fabio.estevam@nxp.com> CC: Akshay Bhat <akshaybhat@timesys.com> CC: Ken Lin <Ken.Lin@advantech.com.tw> CC: Marek Vasut <marek.vasut@gmail.com> CC: Heiko Schocher <hs@denx.de> CC: "Sébastien Szymanski" <sebastien.szymanski@armadeus.com> CC: Christian Gmeiner <christian.gmeiner@gmail.com> CC: Stefan Roese <sr@denx.de> CC: Patrick Bruenn <p.bruenn@beckhoff.com> CC: Troy Kisky <troy.kisky@boundarydevices.com> CC: Nikita Kiryanov <nikita@compulab.co.il> CC: Otavio Salvador <otavio@ossystems.com.br> CC: "Eric Bénard" <eric@eukrea.com> CC: Jagan Teki <jagan@amarulasolutions.com> CC: Ye Li <ye.li@nxp.com> CC: Peng Fan <peng.fan@nxp.com> CC: Adrian Alonso <adrian.alonso@nxp.com> CC: Alison Wang <b18965@freescale.com> CC: Tim Harvey <tharvey@gateworks.com> CC: Martin Donnelly <martin.donnelly@ge.com> CC: Marcin Niestroj <m.niestroj@grinn-global.com> CC: Lukasz Majewski <lukma@denx.de> CC: Adam Ford <aford173@gmail.com> CC: "Albert ARIBAUD (3ADEV)" <albert.aribaud@3adev.fr> CC: Boris Brezillon <boris.brezillon@free-electrons.com> CC: Soeren Moch <smoch@web.de> CC: Richard Hu <richard.hu@technexion.com> CC: Wig Cheng <wig.cheng@technexion.com> CC: Vanessa Maegima <vanessa.maegima@nxp.com> CC: Max Krummenacher <max.krummenacher@toradex.com> CC: Stefan Agner <stefan.agner@toradex.com> CC: Markus Niebel <Markus.Niebel@tq-group.com> CC: Breno Lima <breno.lima@nxp.com> CC: Francesco Montefoschi <francesco.montefoschi@udoo.org> CC: Jaehoon Chung <jh80.chung@samsung.com> CC: Scott Wood <oss@buserror.net> CC: Joe Hershberger <joe.hershberger@ni.com> CC: Anatolij Gustschin <agust@denx.de> CC: Simon Glass <sjg@chromium.org> CC: "Andrew F. Davis" <afd@ti.com> CC: "Łukasz Majewski" <l.majewski@samsung.com> CC: Patrice Chotard <patrice.chotard@st.com> CC: Nobuhiro Iwamatsu <iwamatsu@nigauri.org> CC: Hans de Goede <hdegoede@redhat.com> CC: Masahiro Yamada <yamada.masahiro@socionext.com> CC: Stephen Warren <swarren@nvidia.com> CC: Andre Przywara <andre.przywara@arm.com> CC: "Álvaro Fernández Rojas" <noltari@gmail.com> CC: York Sun <york.sun@nxp.com> CC: Xiaoliang Yang <xiaoliang.yang@nxp.com> CC: Chen-Yu Tsai <wens@csie.org> CC: George McCollister <george.mccollister@gmail.com> CC: Sven Ebenfeld <sven.ebenfeld@gmail.com> CC: Filip Brozovic <fbrozovic@gmail.com> CC: Petr Kulhavy <brain@jikos.cz> CC: Eric Nelson <eric@nelint.com> CC: Bai Ping <ping.bai@nxp.com> CC: Anson Huang <Anson.Huang@nxp.com> CC: Sanchayan Maity <maitysanchayan@gmail.com> CC: Lokesh Vutla <lokeshvutla@ti.com> CC: Patrick Delaunay <patrick.delaunay@st.com> CC: Gary Bisson <gary.bisson@boundarydevices.com> CC: Alexander Graf <agraf@suse.de> CC: u-boot@lists.denx.de Reviewed-by: NFabio Estevam <fabio.estevam@nxp.com> Reviewed-by: NChristian Gmeiner <christian.gmeiner@gmail.com>
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- 07 9月, 2016 1 次提交
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由 Fabio Estevam 提交于
Currently MX6 SPL DDR initialization hardcodes the REF_SEL and REFR fields of the MDREF register as 1 and 7, respectively for DDR3 and 0 and 3 for LPDDR2. Looking at the MDREF initialization done via DCD we see that boards do need to initialize these fields differently: $ git grep 0x021b0020 board/ board/bachmann/ot1200/mx6q_4x_mt41j128.cfg:DATA 4 0x021b0020 0x00005800 board/ccv/xpress/imximage.cfg:DATA 4 0x021b0020 0x00000800 /* MMDC0_MDREF */ board/freescale/mx6qarm2/imximage.cfg:DATA 4 0x021b0020 0x7800 board/freescale/mx6qarm2/imximage.cfg:DATA 4 0x021b0020 0x00005800 board/freescale/mx6qarm2/imximage_mx6dl.cfg:DATA 4 0x021b0020 0x00005800 board/freescale/mx6qarm2/imximage_mx6dl.cfg:DATA 4 0x021b0020 0x00005800 board/freescale/mx6qsabreauto/imximage.cfg:DATA 4 0x021b0020 0x00005800 board/freescale/mx6qsabreauto/mx6dl.cfg:DATA 4 0x021b0020 0x00005800 board/freescale/mx6qsabreauto/mx6qp.cfg:DATA 4 0x021b0020 0x00005800 board/freescale/mx6sabresd/mx6dlsabresd.cfg:DATA 4 0x021b0020 0x00005800 board/freescale/mx6sabresd/mx6q_4x_mt41j128.cfg:DATA 4 0x021b0020 0x00005800 board/freescale/mx6slevk/imximage.cfg:DATA 4 0x021b0020 0x00001800 board/freescale/mx6sxsabreauto/imximage.cfg:DATA 4 0x021b0020 0x00000800 board/freescale/mx6sxsabresd/imximage.cfg:DATA 4 0x021b0020 0x00000800 board/warp/imximage.cfg:DATA 4 0x021b0020 0x00001800 So introduce a mechanism for users to be able to configure REFSEL and REFR fields as needed. Keep all the mx6 SPL users in their current REF_SEL and REFR values, so no functional changes for the existing users. Signed-off-by: NFabio Estevam <fabio.estevam@nxp.com> Reviewed-by: NEric Nelson <eric@nelint.com>
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- 19 11月, 2015 1 次提交
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由 Nikita Kiryanov 提交于
Use spl alternate boot device feature to define fallback to the main boot device as it is defined by hardware. Signed-off-by: NNikita Kiryanov <nikita@compulab.co.il> Cc: Igor Grinberg <grinberg@compulab.co.il> Cc: Stefano Babic <sbabic@denx.de> Cc: Tom Rini <trini@konsulko.com> Reviewed-by: NTom Rini <trini@konsulko.com> Reviewed-by: NStefano Babic <sbabic@denx.de>
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- 10 7月, 2015 1 次提交
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由 Peng Fan 提交于
enable_spi_clock does the same thing with enable_cspi_clock, so remove enable_cspi_clock. Remove enable_cspi_clock prototype in header file convert cm_fx6/spl.c to use enable_spi_clk Signed-off-by: NPeng Fan <Peng.Fan@freescale.com> Acked-by: NStefano Babic <sbabic@denx.de>
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- 20 1月, 2015 1 次提交
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由 Simon Glass 提交于
The global_data pointer (gd) has already been set before board_init_f() is called. We should not assign it again. We should also not use gdata since it is going away. Signed-off-by: NSimon Glass <sjg@chromium.org> Acked-by: NIgor Grinberg <grinberg@compulab.co.il> Tested-by: NNikita Kiryanov <nikita@compulab.co.il> Acked-by: NNikita Kiryanov <nikita@compulab.co.il>
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- 06 11月, 2014 1 次提交
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由 Nikita Kiryanov 提交于
The 1GB DRAM configuration on mx6 solo uses 2 chip selects, but the code tests 1GB DRAM configuration as if it is all present on one chip select, and thus cannot see the full range of available memory. Refactor the check to detect 1GB DRAM correctly. Signed-off-by: NNikita Kiryanov <nikita@compulab.co.il> Cc: Igor Grinberg <grinberg@compulab.co.il> Cc: Stefano Babic <sbabic@denx.de> Acked-by: NIgor Grinberg <grinberg@compulab.co.il>
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- 09 9月, 2014 2 次提交
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由 Nikita Kiryanov 提交于
Add NAND support for Compulab CM-FX6 CoM. Cc: Igor Grinberg <grinberg@compulab.co.il> Cc: Stefano Babic <sbabic@denx.de> Cc: Tom Rini <trini@ti.com> Acked-by: NIgor Grinberg <grinberg@compulab.co.il> Signed-off-by: NNikita Kiryanov <nikita@compulab.co.il>
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由 Nikita Kiryanov 提交于
Add initial support for Compulab CM-FX6 CoM. Support includes MMC, SPI flash, and SPL with dynamic DRAM detection. Cc: Igor Grinberg <grinberg@compulab.co.il> Cc: Stefano Babic <sbabic@denx.de> Cc: Tom Rini <trini@ti.com> Cc: Marek Vasut <marex@denx.de> Cc: Simon Glass <sjg@chromium.org> Acked-by: NMarek Vasut <marex@denx.de> Signed-off-by: NNikita Kiryanov <nikita@compulab.co.il>
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