- 27 12月, 2012 1 次提交
-
-
由 Fabio Estevam 提交于
Since commit c7336815 (pmic: Extend PMIC framework to support multiple instances of PMIC devices) mx53loco fails to allocate the memory for PMIC: U-Boot 2013.01-rc2-dirty (Dec 20 2012 - 15:55:01) Board: MX53 LOCO I2C: ready DRAM: 1 GiB pmic_alloc: No available memory for allocation! pmic_init: POWER allocation error! CPU: Freescale i.MX53 family rev2.0 at 800 MHz Reset cause: POR MMC: FSL_SDHC: 0, FSL_SDHC: 1 Calling the PMIC related functions at a later stage, ie, from board_late_init() fixes the issue. Reported-by: NRobert Nelson <robertcnelson@gmail.com> Signed-off-by: NFabio Estevam <fabio.estevam@freescale.com> Tested-by: NStefano Babic <sbabic@denx.de>
-
- 26 12月, 2012 5 次提交
-
-
由 Otavio Salvador 提交于
This allow use of mainline and Freescale BSP Linux kernel with same environment. Signed-off-by: NOtavio Salvador <otavio@ossystems.com.br>
-
由 Otavio Salvador 提交于
This allow use of mainline and Freescale BSP Linux kernel with same environment. Signed-off-by: NOtavio Salvador <otavio@ossystems.com.br>
-
由 Otavio Salvador 提交于
This allow use of mainline and Freescale BSP Linux kernel with same environment. Signed-off-by: NOtavio Salvador <otavio@ossystems.com.br>
-
由 Otavio Salvador 提交于
For a generic environment, we shouldn't have a fixed rootfs filesystem so we drop it from env. Signed-off-by: NOtavio Salvador <otavio@ossystems.com.br>
-
由 Fabio Estevam 提交于
Select CONFIG_OF_LIBFDT, so that a dt kernel can be launched. Signed-off-by: NFabio Estevam <fabio.estevam@freescale.com>
-
- 13 12月, 2012 2 次提交
-
-
由 Fabio Estevam 提交于
Select CONFIG_OF_LIBFDT so that a device tree kernel can be launched. Signed-off-by: NFabio Estevam <fabio.estevam@freescale.com>
-
由 Fabio Estevam 提交于
commit c7336815 (pmic: Extend PMIC framework to support multiple instances of PMIC devices) has incorrectly passed the PMIC name under the FSL PMIC case. Fix that by passing "FSL_PMIC" as the parameter of pmic_get. Signed-off-by: NFabio Estevam <fabio.estevam@freescale.com>
-
- 12 12月, 2012 2 次提交
-
-
由 Fabio Estevam 提交于
Set the gpio value in gpio_direction_output() instead of an extra gpio_set_value call. Signed-off-by: NFabio Estevam <fabio.estevam@freescale.com> Acked-by: NStefano Babic <sbabic@denx.de>
-
由 Fabio Estevam 提交于
Make the necessary adaptions for the new PMIC framework, so that mx25pdk can be built again. Signed-off-by: NFabio Estevam <fabio.estevam@freescale.com> Acked-by: NStefano Babic <sbabic@denx.de>
-
- 08 12月, 2012 1 次提交
-
-
git://git.denx.de/u-boot由 Stefano Babic 提交于
Conflicts: drivers/power/power_fsl.c include/configs/mx35pdk.h include/configs/mx53loco.h include/configs/woodburn_common.h board/woodburn/woodburn.c These boards still use the old old PMIC framework, so they do not merge properly after the power framework was merged into mainline. Fix all conflicts and update woodburn to use Power Framework. Signed-off-by: NStefano Babic <sbabic@denx.de>
-
- 07 12月, 2012 29 次提交
-
-
-
由 Łukasz Majewski 提交于
The filename buffer is allocated dynamically. It must be cache aligned. Moreover, it is necessary to erase its content before we use it for file name operations. This prevents from corruption of written file names. Signed-off-by: NLukasz Majewski <l.majewski@samsung.com> Signed-off-by: NKyungmin Park <kyungmin.park@samsung.com>
-
由 Łukasz Majewski 提交于
Several fixes to suppress compiler's (eldk-5.[12].x gcc 4.6) warning [-Wunused-but-set-variable] Signed-off-by: NLukasz Majewski <l.majewski@samsung.com> Signed-off-by: NKyungmin Park <kyungmin.park@samsung.com>
-
由 Łukasz Majewski 提交于
The device block descriptor (block_dev_desc_t) )shall be stored at ext4 early code (at ext4fs_set_blk_dev in this case) to be available for latter use (like put_ext4()). Signed-off-by: NLukasz Majewski <l.majewski@samsung.com> Signed-off-by: NKyungmin Park <kyungmin.park@samsung.com>
-
由 Łukasz Majewski 提交于
The ext4write code has been using direct calls to 64-32 division (/ and %). Officially supported u-boot toolchains (eldk-5.[12].x) generate calls to __aeabi_uldivmod(), which is niether defined in the toolchain libs nor u-boot source tree. Due to that, when the ext4write command has been executed, "undefined instruction" execption was generated (since the __aeabi_uldivmod() is not provided). To fix this error, lldiv() for division and do_div() for modulo have been used. Those two functions are recommended for performing 64-32 bit number division in u-boot. Signed-off-by: NLukasz Majewski <l.majewski@samsung.com> Signed-off-by: NKyungmin Park <kyungmin.park@samsung.com>
-
由 Luka Perkov 提交于
Change e-mail address of Luka Perkov. Signed-off-by: NLuka Perkov <luka@openwrt.org> CC: Luka Perkov <uboot@lukaperkov.net>
-
由 Joshua Housh 提交于
If the pl011 is connected to another device which has hardware flow-control on, characters are never received by the pl011. Asserting RTS when flow-control is off will have no effect. This is in line with how Linux behaves. Signed-off-by: NJoshua Housh <joshua.housh@calxeda.com> Tested-by: NMarek Vasut <marex@denx.de>
-
由 Robert P. J. Day 提交于
Since there's no obvious mention, add a brief reference to the custodians page at www.denx.de Signed-off-by: NRobert P. J. Day <rpjday@crashcourse.ca>
-
由 Otavio Salvador 提交于
Use a generic 'dram_vals[]' array that has the full initialization sequence and rename the initialization method so it doesn't has a frequency on its name. Signed-off-by: NOtavio Salvador <otavio@ossystems.com.br>
-
由 Simon Glass 提交于
The config is current broken. It compiles but does not boot because IDE is enabled. Remove all IDE options, and enable SCSI instead. Also add a working boot command and Linux bootargs, and enable command line editing to make it easier to work with. Signed-off-by: NSimon Glass <sjg@chromium.org>
-
由 Gabe Black 提交于
This allows u-boot to figure out the partitions of a chrome-os install. Signed-off-by: NGabe Black <gabeblack@chromium.org> Signed-off-by: NSimon Glass <sjg@chromium.org>
-
由 Simon Glass 提交于
Enable the display on coreboot, using CFB. Signed-off-by: NSimon Glass <sjg@chromium.org>
-
由 Simon Glass 提交于
When running from coreboot we don't want this code, so make it optional. Signed-off-by: NSimon Glass <sjg@chromium.org>
-
由 Simon Glass 提交于
This function is not intended to be exported from the video drivers, so remove the prototype. This fixes an error: cfb_console.c:1793:12: error: static declaration of 'video_init' follows non-static declaration Signed-off-by: NSimon Glass <sjg@chromium.org>
-
由 Duncan Laurie 提交于
This command will start erasing at memory address zero if there is not a valid framebuffer address that was found during video_init(). This is a common case with Chrome OS devices in normal mode when we do not execute the video option rom in coreboot. Signed-off-by: NDuncan Laurie <dlaurie@chromium.org> Signed-off-by: NSimon Glass <sjg@chromium.org>
-
由 Stefan Reinauer 提交于
The function setup_pcat_compatibility() is weak and implemented as empty function in board.c hence we don't have to override that with another empty function. monitor_flash_len is unused, drop it. Signed-off-by: NStefan Reinauer <reinauer@chromium.org> Signed-off-by: NSimon Glass <sjg@chromium.org>
-
由 Stefan Reinauer 提交于
... because that information is already "encoded" in the directory name. Signed-off-by: NStefan Reinauer <reinauer@chromium.org> Signed-off-by: NSimon Glass <sjg@chromium.org>
-
由 Vadim Bendebury 提交于
Some systems (like Google Link device) provide the ability to keep a history of the target CPU port80 accesses, which is extremely handy for debugging. The problem is that the EC handling port 80 access is orders of magnitude slower than the AP. This causes random loss of trace data. This change allows to throttle port 80 accesses such that in case the AP is trying to post faster than the EC can handle, a delay is introduced to make sure that the post rate is throttled. Experiments have shown that on Link the delay should be at least 350,000 of tsc clocks. Throttling is not being enabled by default: to enable it one would have to set MIN_PORT80_KCLOCKS_DELAY to something like 400 and rebuild the u-boot image. With upcoming EC code optimizations this number could be decreased (new new value should be established experimentally). Signed-off-by: NVadim Bendebury <vbendeb@chromium.org> Signed-off-by: NSimon Glass <sjg@chromium.org>
-
由 Vadim Bendebury 提交于
Some u-boot modules rely on availability of get_ticks() and get_tbclk() functions, reporting a free running clock and its frequency respectively. Traditionally these functions return number and frequency of timer interrupts. Intel's core architecture processors however are known to run the rdtsc instruction at a constant rate of the so called 'Max Non Turbo ratio' times the external clock frequency which is 100MHz. This is just as good for the timer tick functions in question. Signed-off-by: NVadim Bendebury <vbendeb@chromium.org> Signed-off-by: NSimon Glass <sjg@chromium.org>
-
由 Duncan Laurie 提交于
This will write magic value to APMC command port which will trigger an SMI and cause coreboot to lock down the ME, chipset, and CPU. Signed-off-by: NDuncan Laurie <dlaurie@chromium.org> Signed-off-by: NSimon Glass <sjg@chromium.org>
-
由 Duncan Laurie 提交于
Coreboot was always using MTRR 7 for the write-protect cache entry that covers the ROM and U-boot was removing it. However with 4GB configs we need more MTRRs for the BIOS and so the WP MTRR needs to move. Instead coreboot will always use the last available MTRR that is normally set aside for OS use and U-boot can clear it before the OS. Signed-off-by: NDuncan Laurie <dlaurie@chromium.org> Signed-off-by: NSimon Glass <sjg@chromium.org>
-
由 Stefan Reinauer 提交于
This helps us monitor boot progress and determine where U-Boot dies if there are any problems. Signed-off-by: NStefan Reinauer <reinauer@google.com> Signed-off-by: NSimon Glass <sjg@chromium.org>
-
由 Simon Glass 提交于
This contains just the minimum information for a coreboot-based board. Signed-off-by: NStefan Reinauer <reinauer@chromium.org> Signed-off-by: NGabe Black <gabeblack@chromium.org> Signed-off-by: NSimon Glass <sjg@chromium.org>
-
由 Gabe Black 提交于
We will use coreboot.dtsi as our fdt include file. Signed-off-by: NGabe Black <gabeblack@chromium.org> Signed-off-by: NSimon Glass <sjg@chromium.org>
-
由 Gabe Black 提交于
Allow a device tree to be provided through the standard mechanisms. Signed-off-by: NGabe Black <gabeblack@google.com> Signed-off-by: NSimon Glass <sjg@chromium.org>
-
由 Stefan Reinauer 提交于
This option delays loading of the environment until later, so that only the default environment will be available to U-Boot. This can address the security risk of untrusted data being used during boot. When CONFIG_DELAY_ENVIRONMENT is defined, it is convenient to have a run-time way of enabling loadinlg of the environment. Add this to the fdt as /config/delay-environment. Note: This patch depends on http://patchwork.ozlabs.org/patch/194342/Signed-off-by: NSimon Glass <sjg@chromium.org> Signed-off-by: NStefan Reinauer <reinauer@chromium.org>
-
由 Gabe Black 提交于
These were removed, but actually are useful. Cold means that we started from a reset/power on. Warm means that we started from another U-Boot. We determine whether u-boot on x86 was warm or cold booted (really if it started at the beginning of the text segment or at the ELF entry point). We plumb the result through to the global data structure. Signed-off-by: NSimon Glass <sjg@chromium.org>
-
由 Gabe Black 提交于
Because calculate_relocation_address now uses the e820 map, it will be able to avoid addresses over 32 bits and regions that are at high addresses but not big enough for U-Boot. It also means we can remove the hack which limitted U-Boot's idea of the size of memory to less than 4GB. Also take into account the space needed for the heap and stack, so we avoid picking a very small region those areas might overlap with something it shouldn't. Signed-off-by: NGabe Black <gabeblack@chromium.org> Signed-off-by: NSimon Glass <sjg@chromium.org>
-
由 Gabe Black 提交于
Different systems may have different mechanisms for picking a suitable place to relocate U-Boot to. Signed-off-by: NGabe Black <gabeblack@chromium.org> Signed-off-by: NSimon Glass <sjg@chromium.org>
-