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  1. 02 9月, 2021 1 次提交
    • P
      armv8: Disable pointer authentication traps for EL1 · 53b40e8d
      由 Peter Hoyes 提交于 
      The use of ARMv8.3 pointer authentication (PAuth) is governed by fields
in HCR_EL2, which trigger a 'trap to EL2' if not enabled. The reset
value of these fields is 'architecturally unknown' so we must ensure
that the fields are enabled (to disable the traps) if we are entering
the kernel at EL1.

The APK field disables PAuth instruction traps and the API field
disables PAuth register traps

Add code to disable the traps in armv8_switch_to_el1_m. Prior to doing
so, it checks fields in the ID_AA64ISAR1_EL1 register to ensure pointer
authentication is supported by the hardware.

The runtime checks require a second temporary register, so add this to
the EL1 transition macro signature and update 2 call sites.
Signed-off-by: NPeter Hoyes <Peter.Hoyes@arm.com>
      53b40e8d
  3. 01 9月, 2021 1 次提交
    • T
      Convert CONFIG_SKIP_LOWLEVEL_INIT et al to Kconfig · a2ac2b96
      由 Tom Rini 提交于 
      This converts the following to Kconfig:
   CONFIG_SKIP_LOWLEVEL_INIT
   CONFIG_SKIP_LOWLEVEL_INIT_ONLY

In order to do this, we need to introduce SPL and TPL variants of these
options so that we can clearly disable these options only in SPL in some
cases, and both instances in other cases.
Signed-off-by: NTom Rini <trini@konsulko.com>
      a2ac2b96
  5. 31 8月, 2021 3 次提交
  7. 09 8月, 2021 18 次提交
  9. 01 8月, 2021 1 次提交
  11. 29 7月, 2021 2 次提交
  13. 24 7月, 2021 1 次提交
    • P
      armv8: Initialize CNTFRQ if at highest exception level · c48fec6e
      由 Peter Hoyes 提交于 
      CNTFRQ_EL0 is only writable from the highest supported exception
level on the platform. For Armv8-A, this is typically EL3, but
technically EL2 and EL3 are optional so it may need to be
initialized at EL2 or EL1. For Armv8-R, the highest exception
level is always EL2.

This patch moves the initialization outside of the switch_el
block and uses a new macro branch_if_not_highest_el which
dynamically detects whether it is at the highest supported
exception level.

Linux's docs state that CNTFRQ_EL0 should be initialized by the
bootloader. If not set, the the U-Boot prompt countdown hangs.
Signed-off-by: NPeter Hoyes <Peter.Hoyes@arm.com>
      c48fec6e
  15. 17 7月, 2021 1 次提交
  17. 15 7月, 2021 3 次提交
  19. 10 7月, 2021 4 次提交
    • T
      pci: imx: use reset-gpios if defined by device-tree · c1f6fd2b
      由 Tim Harvey 提交于 
      If reset-gpio is defined by device-tree use that if
CONFIG_PCIE_IMX_PERST_GPIO is not defined.

Note that after this the following boards which define
CONFIG_PCIE_IMX_PERST_GPIO in their board header file as well as their
device-tree should be able to remove CONFIG_PCIE_IMX_PERST_GPIO without
consequence:
 - mx6sabresd
 - mx6sxsabresd
 - novena
 - tbs2910
 - vining_2000

Note that the ge_bx50v3 board uses CONFIG_PCIE_IMX_PERST_GPIO and does
not have reset-gpios defined it it's pcie node in the dt thus removing
CONFIG_PCIE_IMX_PERST_GPIO globally can't be done until that board adds
reset-gpios.

Cc: Ian Ray <ian.ray@ge.com> (maintainer:GE BX50V3 BOARD)
Cc: Sebastian Reichel <sebastian.reichel@collabora.com> (maintainer:GE BX50V3 BOARD)
Cc: Fabio Estevam <festevam@gmail.com> (maintainer:MX6SABRESD BOARD)
Cc: Marek Vasut <marex@denx.de> (maintainer:NOVENA BOARD)
Cc: Soeren Moch <smoch@web.de> (maintainer:TBS2910 BOARD)
Cc: Silvio Fricke <open-source@softing.de> (maintainer:VINING_2000 BOARD)
Signed-off-by: NTim Harvey <tharvey@gateworks.com>
      c1f6fd2b
    • A
      mmc: sunxi: Increase MMIO FIFO read performance · 9faae545
      由 Andre Przywara 提交于 
      To avoid the complexity of DMA operations (with chained descriptors), we
use repeated MMIO reads and writes to the SD_FIFO_REG, which allows us
to drain or fill the MMC data buffer FIFO very easily.

However those MMIO accesses are somewhat costly, so this limits our MMC
performance, to between 17 and 22 MB/s, but down to 9.5 MB/s on the H6
(partly due to the lower AHB1 frequency).

As it turns out we read the FIFO status register after *every* word we
read or write, which effectively doubles the number of MMIO accesses,
thus effectively more than halving our performance.

To avoid this overhead, we can make use of the FIFO level bits, which are
in the very same FIFO status registers.
So for a read request, we now can collect as many words as the FIFO
level originally indicated, and only then need to update the status
register.

We don't know for sure the size of the FIFO (and it seems to differ
across SoCs anyway), so writing is more fragile, which is why we still
use the old method for that. If we find a minimum FIFO size available on
all SoCs, we could use that, in a later optimisation.

This patch increases the eMMC read speed on a Pine64-LTS from about
22MB/s to 44 MB/s. SD card reads don't gain that much, but with 23 MB/s
we now reach the practical limit for 3.3V SD cards.
On the H6 we double our transfer speed, from 9.5 MB/s to 19.7 MB/s.
Signed-off-by: NAndre Przywara <andre.przywara@arm.com>
      9faae545
    • A
      mmc: sunxi: Fix MMC clock parent selection · 937ee31e
      由 Andre Przywara 提交于 
      Most Allwinner SoCs which use the so called "new timing mode" in their
MMC controllers actually use the double-rate PLL6/PERIPH0 clock as their
parent input clock. This is interestingly enough compensated by a hidden
"by 2" post-divider in the mod clock, so the divider and actual output
rate stay the same.

Even though for the H6 and H616 (but only for them!) we use the doubled
input clock for the divider computation, we never accounted for the
implicit post-divider, so the clock was only half the speed on those SoCs.
This didn't really matter so far, as our slow MMIO routine limits the
transfer speed anyway, but we will fix this soon.

Clean up the code around that selection, to always use the normal PLL6
(PERIPH0(1x)) clock as an input. As the rate and divider are the same,
that makes no difference.
Explain the hardware differences in a comment.
Signed-off-by: NAndre Przywara <andre.przywara@arm.com>
      937ee31e
    • A
      sunxi: clock: H6/H616: Fix PLL clock factor encodings · f9d13247
      由 Andre Przywara 提交于 
      Most clock factors and dividers in the H6 PLLs use a "+1 encoding",
which we were missing on two occasions.

This fixes the MMC clock setup on the H6, which could be slightly off due
to the wrong parent frequency:
mmc 2 set mod-clk req 52000000 parent 1176000000 n 2 m 12 rate 49000000

Also the CPU frequency (PLL1) was a tad too high before.

For PLL5 (DRAM) we already accounted for this +1, but in the DRAM code
itself, not in the bit field macro. Move this there to be aligned with
what the other SoCs and other PLLs do.
Signed-off-by: NAndre Przywara <andre.przywara@arm.com>
Reviewed-by: NJernej Skrabec <jernej.skrabec@gmail.com>
      f9d13247
  21. 08 7月, 2021 4 次提交
  23. 07 7月, 2021 1 次提交