Force master mode on the A20-OLinuXino-Lime2. This change is required
to get a reliable link at gigabit speeds.
Signed-off-by: NMichael Haas <haas@computerlinguist.org>
Acked-by: NHans de Goede <hdegoede@redhat.com>
Signed-off-by: NHans de Goede <hdegoede@redhat.com>

Force master mode for 1000BASE-T operation on the
A20-Olimex-SOM-EVB.

Karsten Merker reports that this change is necessary to get a reliable
link at gigabit speeds.
Signed-off-by: NMichael Haas <haas@computerlinguist.org>
Acked-by: NHans de Goede <hdegoede@redhat.com>
Signed-off-by: NHans de Goede <hdegoede@redhat.com>

This patch introduces CONFIG_RTL8211X_PHY_FORCE_MASTER. If this
define is set, RTL8211x PHYs (except for the RTL8211F) will have their
1000BASE-T master/slave autonegotiation disabled and forced to master
mode.

This is helpful for PHYs like the RTL8211C which produce unstable links
in slave mode. Such problems have been found on the A20-Olimex-SOM-EVB
and A20-OLinuXino-Lime2.

There is no proper way to identify affected PHYs in software as the
RTL8211C shares its UID with the RTL8211B. Thus, this fix requires
the introduction of an #ifdef.

CC: fradav@gmail.com
CC: merker@debian.org
CC: hdegoede@redhat.com
CC: ijc@hellion.org.uk
CC: joe.hershberger@ni.com
Signed-off-by: NMichael Haas <haas@computerlinguist.org>
Tested-by: NKarsten Merker <merker@debian.org>
Acked-by: NJoe Hershberger <joe.hershberger@ni.com>
Signed-off-by: NHans de Goede <hdegoede@redhat.com>

As the need for various magic sram pokes has shown this maybe useful
info to have. e.g. this shows one of my a23 tablets having an id of
1661 rather then the usual 1650 for the a23.
Signed-off-by: NHans de Goede <hdegoede@redhat.com>
Acked-by: NIan Campbell <ijc@hellion.org.uk>

I noticed that for certain SoC versions boot0 does a magic poke when
build for A33. I'm not aware of this actually being necessary anywhere,
but better safe then sorry.
Signed-off-by: NHans de Goede <hdegoede@redhat.com>
Acked-by: NIan Campbell <ijc@hellion.org.uk>

This bit needs to be set for system suspend/resume to work. This setting
will be documented in an updated TRM at some time in the future.
Signed-off-by: NStephen Warren <swarren@nvidia.com>
Signed-off-by: NTom Warren <twarren@nvidia.com>

This patch enable VID support for ls2080ardb platform.
It uses the common VID driver.
Signed-off-by: NRai Harninder <harninder.rai@nxp.com>
Reviewed-by: NYork Sun <york.sun@nxp.com>

Clock phase and polarity for DSPI flash need to be set.
Signed-off-by: NGong Qianyu <Qianyu.Gong@nxp.com>
Reviewed-by: NYork Sun <york.sun@nxp.com>

Signed-off-by: NMingkai Hu <mingkai.hu@nxp.com>
Signed-off-by: NGong Qianyu <Qianyu.Gong@nxp.com>
Reviewed-by: NYork Sun <york.sun@nxp.com>

Signed-off-by: NMingkai Hu <mingkai.hu@nxp.com>
Signed-off-by: NGong Qianyu <Qianyu.Gong@nxp.com>
Reviewed-by: NYork Sun <york.sun@nxp.com>

Use a pointer to pass image address to fsl_secboot_validate(),
instead of using environmental variable "img_addr".
Signed-off-by: NAneesh Bansal <aneesh.bansal@nxp.com>
Signed-off-by: NSaksham Jain <saksham.jain@nxp.com>
Reviewed-by: NYork Sun <york.sun@nxp.com>

In case of fatal failure during secure boot execution (e.g. header
not found), reset is asserted to stop execution. If the RESET_REQ
is not tied to HRESET, this allows the execution to continue.

Add esbh_halt() after the reset to make sure execution stops.
Signed-off-by: NAneesh Bansal <aneesh.bansal@nxp.com>
Signed-off-by: NSaksham Jain <saksham.jain@nxp.com>
Reviewed-by: NYork Sun <york.sun@nxp.com>

For secure boot, currently we were using fixed bootargs for all SoCs.
This is not needed and we can use the bootargs which are used in
non-secure boot.
Signed-off-by: NAneesh Bansal <aneesh.bansal@nxp.com>
Signed-off-by: NSaksham Jain <saksham.jain@nxp.com>
Reviewed-by: NYork Sun <york.sun@nxp.com>

This commit solves CAAM coherency issue on ls2080. When caches are
enabled and CAAM's DMA's AXI transcations are not made cacheable,
Core reads/writes data from/to caches and CAAM does from main memory.
This forces data flushes to synchronize various data structures. But
even if any data in proximity of these structures is read by core,
these structures again are fetched in caches.

To avoid this problem, either all the data that CAAM accesses can be
made cache line aligned or CAAM transcations can be made cacheable.

So, this commit makes CAAM transcations as write back with write and
read allocate.
Signed-off-by: NSaksham Jain <saksham.jain@nxp.com>
Reviewed-by: NYork Sun <york.sun@nxp.com>

When MMU is disabled, 64-bit write must be aligned at 64-bit
boundary. Becaue the memory location is not guaranteed to be 64-bit
aligned, the 64-bit write needs to be split into two 32-bit writes
to avoid the alignment exception.
Signed-off-by: NAneesh Bansal <aneesh.bansal@nxp.com>
Signed-off-by: NSaksham Jain <saksham.jain@nxp.com>
Reviewed-by: NYork Sun <york.sun@nxp.com>

During secure boot, SMMU is enabled on POR by SP bootrom. SMMU needs
to be put in bypass mode in uboot to enable CAAM transcations to pass
through.

For non-secure boot, SP BootROM doesn't enable SMMU, which is in
bypass mode out of reset.
Signed-off-by: NAneesh Bansal <aneesh.bansal@nxp.com>
Signed-off-by: NSaksham Jain <saksham.jain@nxp.com>
Reviewed-by: NYork Sun <york.sun@nxp.com>

The GUR (DCFG) registers in CCSR space are in little endian format.
Define a config CONFIG_SYS_FSL_CCSR_GUR_LE in
arch/arm/include/asm/arch-fsl-layerscape/config.h
Signed-off-by: NAneesh Bansal <aneesh.bansal@nxp.com>
Signed-off-by: NSaksham Jain <saksham.jain@nxp.com>
Reviewed-by: NYork Sun <york.sun@nxp.com>

"fdt_high" env variable was set to 0xcfffffff for secure boot.
Change it to 0xa0000000 for LS2080 to be consistent with non-secure
boot targets.
Signed-off-by: NAneesh Bansal <aneesh.bansal@nxp.com>
Signed-off-by: NSaksham Jain <saksham.jain@nxp.com>
Reviewed-by: NYork Sun <york.sun@nxp.com>

To unify steps for secure boot for xip (eg. NOR) and non-xip memories
(eg. NAND, SD), bootscipts and its header are copied to main memory.
Validation and execution are performed from there.

For other ARM Platforms (ls1043 and ls1020), to avoid disruption of
existing users, this copy step is not used for NOR boot.
Signed-off-by: NAneesh Bansal <aneesh.bansal@nxp.com>
Signed-off-by: NSaksham Jain <saksham.jain@nxp.com>
Reviewed-by: NYork Sun <york.sun@nxp.com>

During secure boot, Linux image along with other images are validated
using bootscript. This bootscript also needs to be validated before
it executes. This requires a header for bootscript.

When secure boot is enabled, default bootcmd is changed to first
validate bootscript using the header and then execute the script.

For ls2080, NOR memory map is different from other ARM SoCs. So a new
address on NOR is used for this bootscript header (0x583920000). The
Bootscript address is mentioned in this header along with addresses of
other images.
Signed-off-by: NAneesh Bansal <aneesh.bansal@nxp.com>
Signed-off-by: NSaksham Jain <saksham.jain@nxp.com>
Reviewed-by: NYork Sun <york.sun@nxp.com>

Sec_init has been called at the beginning to initialize SEC Block
(CAAM) which is used by secure boot validation later for both ls2080a
qds and rdb. 64-bit address in ESBC Header has been enabled. Secure
boot defconfigs are created for boards (NOR boot).
Signed-off-by: NSaksham Jain <saksham.jain@nxp.com>
Reviewed-by: NYork Sun <york.sun@nxp.com>

For secure boot, a header is used to identify key table, signature
and image address. A new header structure is added for lsch3.

Currently key extension (IE) feature is not supported. Single key
feature is not supported. Keys must be in table format. Hence, SRK
(key table) must be present. Max key number has increase from 4 to
8. The 8th key is irrevocable. A new barker Code is used.
Signed-off-by: NAneesh Bansal <aneesh.bansal@nxp.com>
Signed-off-by: NSaksham Jain <saksham.jain@nxp.com>
Reviewed-by: NYork Sun <york.sun@nxp.com>

Add configs for various IPs used during secure boot. Add address
and endianness for SEC and Security Monitor. SRK are fuses in SFP
(fuses for public key's hash). These are stored in little endian
format.
Signed-off-by: NAneesh Bansal <aneesh.bansal@nxp.com>
Signed-off-by: NSaksham Jain <saksham.jain@nxp.com>
Reviewed-by: NYork Sun <york.sun@nxp.com>

In LS2080, SFP has version 3.4. It is in little endian. The base
address is 0x01e80200. SFP is used in Secure Boot to read fuses.
Signed-off-by: NAneesh Bansal <aneesh.bansal@nxp.com>
Signed-off-by: NSaksham Jain <saksham.jain@nxp.com>
Reviewed-by: NYork Sun <york.sun@nxp.com>

NULL pointer should be checked before any dereference.  This patch
move memest after the NULL pointer check.
Signed-off-by: NPrabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
Reported-by: NJose Rivera <german.rivera@nxp.com>
Acked-by: NJoe Hershberger <joe.hershberger@ni.com>
Reviewed-by: NYork Sun <york.sun@nxp.com>

Free dflt_dpio pointer after its usage during error handling
Signed-off-by: NPrabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
Reported-by: NJose Rivera <german.rivera@nxp.com>
Reviewed-by: NYork Sun <york.sun@nxp.com>

The qspi_cfg register is set by PBI when booting from QSPI. No need
to changing it again.
Signed-off-by: NGong Qianyu <Qianyu.Gong@nxp.com>
Reviewed-by: NYork Sun <york.sun@nxp.com>

Signed-off-by: NGuy Thouret <guy.thouret@wems.co.uk>
Cc: Heiko Schocher <hs@denx.de>

Implement i2c_idle_bus in driver, then setup_i2c can
be dropped for boards which enable DM_I2C/DM_GPIO/PINCTRL.
The i2c_idle_bus force bus idle flow follows setup_i2c in
arch/arm/imx-common/i2c-mxv7.c

This patch is an implementation following linux kernel patch:
"
commit 1c4b6c3bcf30d0804db0d0647d8ebeb862c6f7e5
Author: Gao Pan <b54642@freescale.com>
Date:   Fri Oct 23 20:28:54 2015 +0800

    i2c: imx: implement bus recovery

    Implement bus recovery methods for i2c-imx so we can recover from
    situations where SCL/SDA are stuck low.

    Once i2c bus SCL/SDA are stuck low during transfer, config the i2c
    pinctrl to gpio mode by calling pinctrl sleep set function, and then
    use GPIO to emulate the i2c protocol to send nine dummy clock to recover
    i2c device. After recovery, set i2c pinctrl to default group setting.
"

See Documentation/devicetree/bindings/i2c/i2c-imx.txt for detailed
description.
1. Introuduce scl_gpio/sda_gpio/bus in mxc_i2c_bus.
2. Discard the __weak attribute for i2c_idle_bus and implement it,
   since we have pinctrl driver/driver model gpio driver. We can
   use device tree, but not let board code to do this.
3. gpio state for mxc_i2c is not a must, but it is recommended. If
   there is no gpio state, driver will give tips, but not fail.
4. The i2c controller was first probed, default pinctrl state will
   be used, so when need to use gpio function, need to do
   "pinctrl_select_state(dev, "gpio")" and after force bus idle,
   need to switch back "pinctrl_select_state(dev, "default")".

This is example about how to use the gpio force bus
idle function:
"
 &i2c1 {
 	clock-frequency = <100000>;
	pinctrl-names = "default", "gpio";
 	pinctrl-0 = <&pinctrl_i2c1>;
	pinctrl-1 = <&pinctrl_i2c1_gpio>;
	scl-gpios = <&gpio1 28 GPIO_ACTIVE_HIGH>;
	sda-gpios = <&gpio1 29 GPIO_ACTIVE_HIGH>;
	status = "okay";
	[....]
 };

[.....]

	pinctrl_i2c1_gpio: i2c1grp_gpio {
		fsl,pins = <
			MX6UL_PAD_UART4_TX_DATA__GPIO1_IO28 0x1b8b0
			MX6UL_PAD_UART4_RX_DATA__GPIO1_IO29 0x1b8b0
		>;
	};
"
Signed-off-by: NPeng Fan <van.freenix@gmail.com>
Cc: Albert Aribaud <albert.u.boot@aribaud.net>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Heiko Schocher <hs@denx.de>
Cc: Simon Glass <sjg@chromium.org>
Cc: York Sun <york.sun@nxp.com>

This reverts commit 59deb7fe.
Signed-off-by: NTom Rini <trini@konsulko.com>

This reverts commit 3bc8ffd9.
Signed-off-by: NTom Rini <trini@konsulko.com>

fw_senten/fw_printenv can be compiled as a tools library,
excluding the fw_env_main object.
Reported-by: NStefano Babic <sbabic@denx.de>
Signed-off-by: NAndreas Fenkart <andreas.fenkart@digitalstrom.com>

dma_addr_t holds any valid DMA address. If the DMA API only uses 32-bit
addresses, dma_addr_t need only be 32 bits wide.  Bus addresses, e.g., PCI BARs,
may be wider than 32 bits, but drivers do memory-mapped I/O to ioremapped
kernel virtual addresses, so they don't care about the size of the actual
bus addresses.
Also 32 bit ARM systems with LPAE enabled can use 64bit address space, but
DMA still use 32bit address like in case of DRA7 and Keystone platforms.

This is inspired from the Linux kernel types implementation[1]

[1] https://git.kernel.org/cgit/linux/kernel/git/torvalds/linux.git/tree/include/linux/types.h#n142Acked-by: NLukasz Majewski <l.majewski@samsung.com>
Signed-off-by: NLokesh Vutla <lokeshvutla@ti.com>
Reviewed-by: NTom Rini <trini@konsulko.com>

When switching between EFI context and U-Boot context we need to swap
the register that "gd" resides in.

Some functions slipped through here, with efi_allocate_pool / efi_free_pool
not doing the switch correctly and efi_return_handle switching too often.

Fix them all up to make sure we always have consistent register state.
Signed-off-by: NAlexander Graf <agraf@suse.de>

Otherwise flash remains in read status mode and it's not possible
to access data on flash.
Signed-off-by: NVasily Khoruzhick <anarsoul@gmail.com>
Acked-by: NStefan Roese <sr@denx.de>

It speeds up loading kernel from SD or USB a lot.
Signed-off-by: NVasily Khoruzhick <anarsoul@gmail.com>
Acked-by: NMarek Vasut <marex@denx.de>

Signed-off-by: NVasily Khoruzhick <anarsoul@gmail.com>

Tested with OHCI and pxafb drivers - no issues found
Signed-off-by: NVasily Khoruzhick <anarsoul@gmail.com>