- 21 9月, 2013 2 次提交
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由 Steve Kipisz 提交于
In Errata 1.0.24, if the board is running at OPP50 and has a warm reset, the boot ROM sets the frequencies for OPP100. This patch attempts to drop the frequencies back to OPP50 as soon as possible in the SPL. Then later the voltages and frequencies up set higher. Cc: Enric Balletbo i Serra <eballetbo@iseebcn.com> Cc: Lars Poeschel <poeschel@lemonage.de> Signed-off-by: NSteve Kipisz <s-kipisz2@ti.com> [trini: Adapt to current framework] Signed-off-by: NTom Rini <trini@ti.com>
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由 Tom Rini 提交于
Add a am33xx_spl_board_init (and enable the PMICs) that we may see, depending on the board we are running on. In all cases, we see if we can rely on the efuse_sma register to tell us the maximum speed. In the case of Beaglebone White, we need to make sure we are on AC power, and are on later than rev A1, and then we can ramp up to the PG1.0 maximum of 720Mhz. In the case of Beaglebone Black, we are either on PG2.0 that supports 1GHz or PG2.1. As PG2.0 may or may not have efuse_sma set, we cannot rely on this probe. In the case of the GP EVM, EVM SK and IDK we need to rely on the efuse_sma if we are on PG2.1, and the defaults for PG1.0/2.0. Signed-off-by: NTom Rini <trini@ti.com>
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- 20 9月, 2013 5 次提交
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由 Tom Rini 提交于
Starting with PG2.1 we have a register in the CONTROL_MODULE that is set with the package type and maximum supported frequency. Add this, and the relevant mask/values. Signed-off-by: NTom Rini <trini@ti.com>
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由 Tom Rini 提交于
We need to allow for a further call-out in spl_board_init. Call this am33xx_spl_board_init and add a __weak version. This function may be used to scale the MPU frequency up, depending on board needs. Signed-off-by: NTom Rini <trini@ti.com>
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由 Philip, Avinash 提交于
Add a driver for the TPS65910 PMIC that is found in the AM335x GP EVM, AM335x EVM SK and others. Signed-off-by: NPhilip, Avinash <avinashphilip@ti.com> [trini: Split and rework Avinash's changes into new drivers/power framework] Signed-off-by: NTom Rini <trini@ti.com>
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由 Greg Guyotte 提交于
Add a driver for the TPS65217 PMIC that is found in the Beaglebone family of boards. Signed-off-by: NGreg Guyotte <gguyotte@ti.com> [trini: Split and rework Greg's changes into new drivers/power framework] Signed-off-by: NTom Rini <trini@ti.com>
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由 Tom Rini 提交于
We may need to access the PMIC code in SPL, when we have power set. Signed-off-by: NTom Rini <trini@ti.com>
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- 19 9月, 2013 4 次提交
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由 Masahiro Yamada 提交于
Since commit 5dc5f36 removed B2 board support, there are no boards enabling s3c44b0_rtc. Signed-off-by: NMasahiro Yamada <yamada.m@jp.panasonic.com> Cc: Wolfgang Denk <wd@denx.de> Cc: Andrea Scian <andrea.scian@dave-tech.it>
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由 Masahiro Yamada 提交于
Since commit 5dc5f36 removed B2 board support, there are no boards enabling serial_s3c44b0. Signed-off-by: NMasahiro Yamada <yamada.m@jp.panasonic.com> Cc: Wolfgang Denk <wd@denx.de> Cc: Andrea Scian <andrea.scian@dave-tech.it>
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由 Masahiro Yamada 提交于
Since commit 5dc5f36 removed B2 board support, there are no boards enabling s3c44b0_i2c. Signed-off-by: NMasahiro Yamada <yamada.m@jp.panasonic.com> Cc: Wolfgang Denk <wd@denx.de> Cc: Andrea Scian <andrea.scian@dave-tech.it> Acked-by: NHeiko Schocher <hs@denx.de>
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由 Masahiro Yamada 提交于
Because commit 5dc5f36 removed B2 board support, arch/arm/cpu/s3c44b0/* and arch/arm/include/asm/arch-s3c44b0/* are not necessary anymore. Signed-off-by: NMasahiro Yamada <yamada.m@jp.panasonic.com> Cc: Wolfgang Denk <wd@denx.de> Cc: Andrea Scian <andrea.scian@dave-tech.it>
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- 14 9月, 2013 2 次提交
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由 Kuo-Jung Su 提交于
Even though the MMU/D-cache is off, some DMA engines still expect strict address alignment. For example, the incoming Faraday FTMAC110 & FTGMAC100 ethernet controllers expect the tx/rx descriptors should always be aligned to 16-bytes boundary. Signed-off-by: NKuo-Jung Su <dantesu@faraday-tech.com> CC: Albert ARIBAUD <albert.u.boot@aribaud.net>
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由 Masahiro Yamada 提交于
Because the stack pointer is already set in arch/arm/lib/crt0.S, we do not need to set it in arch/arm/lib/spl.c. Signed-off-by: NMasahiro Yamada <yamada.m@jp.panasonic.com>
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- 12 9月, 2013 3 次提交
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由 Tom Rini 提交于
After further testing, this patch has two problems. First, examples/standalone/Makefile was already inherting PLATFORM_LIBS from the top-level Makefile so this lead to duplicating the private libgcc. Second, currently the private libgcc has a reference to 'hang' that is not being fulfilled. This reverts commit 4412db46. Signed-off-by: NTom Rini <trini@ti.com>
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由 Albert ARIBAUD 提交于
Put all informations about targets, including state (active or orphan) and maintainers, in boards.cfg; remove MAINTAINERS; adjust the build system accordingly. Signed-off-by: NAlbert ARIBAUD <albert.u.boot@aribaud.net>
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- 11 9月, 2013 4 次提交
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由 Albert ARIBAUD 提交于
Conflicts: tools/Makefile
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由 Przemyslaw Marczak 提交于
This change allow to use sd card on Goni the same like mmc 0. SD card is mmc dev 1, so it can be used like this: "fatls mmc 1:2". SD card is inited even if eMMC initialization fails. Signed-off-by: NPrzemyslaw Marczak <p.marczak@samsung.com> Signed-off-by: NKyungmin Park <kyungmin.park@samsung.com> CC: Minkyu Kang <mk7.kang@samsung.com> Acked-by: NJaehoon Chung <jh80.chung@samsung.com> Signed-off-by: NMinkyu Kang <mk7.kang@samsung.com>
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由 Przemyslaw Marczak 提交于
On s5pc1xx mmc devices offset is multiply of 0x100000, wrong value was 0x10000. Register offset always points to mmc 0 before this change. Add macro definition of mmc dev register offset to s5pc1xx and exynos mmc. Signed-off-by: NPrzemyslaw Marczak <p.marczak@samsung.com> Signed-off-by: NKyungmin Park <kyungmin.park@samsung.com> CC: Minkyu Kang <mk7.kang@samsung.com> Acked-by: Jaehoon Chung <jh80.chung at samsung.com> Signed-off-by: NMinkyu Kang <mk7.kang@samsung.com>
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由 Chander Kashyap 提交于
As per new convention ARCH_CPU_DTS is not defined in "dtc/Makefile". Hence Arndale comilation is failing. Fix this by adding proper include file in "board/samsung/dts/exynos5250-arndale.dts". Signed-off-by: NChander Kashyap <chander.kashyap@linaro.org> Signed-off-by: NMinkyu Kang <mk7.kang@samsung.com>
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- 09 9月, 2013 4 次提交
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由 Tang Yuantian 提交于
The source clock frequency of I2C bus on p1022 is the platform(CCB) clock, not CCB/2. The wrong source clock frequency leads to wrong I2C bus speed setting. so, fixed it. Signed-off-by: NTang Yuantian <Yuantian.Tang@freescale.com>
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由 Ying Zhang 提交于
- Added section "u_boot_list" in arch/powerpc/cpu/mpc85xx/u-boot-spl.lds - Use the function i2c_init_all instead of i2c_init Signed-off-by: NYing Zhang <b40530@freescale.com>
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- 07 9月, 2013 16 次提交
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由 Stefan Roese 提交于
LCD4 needs a slightly different GPIO configuration than the original LWMON5 variant. GPIO49 needs to be configured to a default output value of 0 (permanent voltage supply). Additionally lcd4 also needs to enable the LSB transmitter. Signed-off-by: NStefan Roese <sr@denx.de>
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由 Masahiro Yamada 提交于
For most boards which define CONFIG_SPL_PAD_TO, it is defined in config header files. Currently, there exists only one exception, cam_enc_4xx board. This patch moves CONFIG_SPL_PAD_TO definition from board/ait/cam_enc_4xx/config.mk to include/configs/cam_enc_4xx.h. With this modification, we can delete a glue code in the top level config.mk: ifneq ($(CONFIG_SPL_PAD_TO),) CPPFLAGS += -DCONFIG_SPL_PAD_TO=$(CONFIG_SPL_PAD_TO) endif Signed-off-by: NMasahiro Yamada <yamada.m@jp.panasonic.com> Cc: Heiko Schocher <hs@denx.de>
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由 Masahiro Yamada 提交于
Currently no makefiles (board-specific config.mk) set the following variables: CONFIG_SPL_TEXT_BASE CONFIG_UBOOT_PAD_TO CONFIG_RESET_VECTOR_ADDRESS CONFIG_TPL_PAD_TO For all target boards using above macros they are set in header files (include/configs/*.h), so we do not need to set them as CPPFLAGS. Signed-off-by: NMasahiro Yamada <yamada.m@jp.panasonic.com>
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由 Oliver Metz 提交于
Signed-off-by: NOliver Metz <oliver@freetz.org> Tested-by: NLuka Perkov <luka@openwrt.org>
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由 Oliver Metz 提交于
Signed-off-by: NOliver Metz <oliver@freetz.org> Tested-by: NLuka Perkov <luka@openwrt.org>
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由 Marek Vasut 提交于
Fix my email address. Signed-off-by: NMarek Vasut <marex@denx.de> Cc: Tom Rini <trini@ti.com>
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由 Henrik Nordström 提交于
Use of uImage formatted u-boot have long been preferred, and recent changes to better support Falcon mode on MMC now enforces it on MMC. Signed-off-by: NHenrik Nordstrom <henrik@henriknordstrom.net>
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由 Rob Herring 提交于
libata already has similar functions as implemented in the ahci code. Refactor the code to use the libata variants and remove the dependency on ata.h. Convert some defines to use the version from libata.h. Also, remove some unnecessary memset's of bss data. This is a step toward hopefully merging ahci.c and dw_ahsata.c which are essentially the same driver. Signed-off-by: NRob Herring <rob.herring@calxeda.com> Reviewed-by: NTom Rini <trini@ti.com>
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由 Rob Herring 提交于
Based on Linux libata code, most drives are less than 10 sec, but some need up to 20 sec. Signed-off-by: NRob Herring <rob.herring@calxeda.com> Reviewed-by: NTom Rini <trini@ti.com>
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由 Rob Herring 提交于
Some Intel SSDs can send a COMINIT after the initial COMRESET. This causes the link to go down and we need to re-initialize the link. Signed-off-by: NRob Herring <rob.herring@calxeda.com>
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由 Rob Herring 提交于
Move the link bring-up handling to a separate weak function in order to allow platforms to override it. This is needed on highbank platform which needs special phy handling. Signed-off-by: NRob Herring <rob.herring@calxeda.com>
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由 Rob Herring 提交于
Replace hard-coded register values with proper defines for PORT_SCR_STAT register. Signed-off-by: NRob Herring <rob.herring@calxeda.com>
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由 Rob Herring 提交于
This fixes a memory leak when scsi inquiry fails. Signed-off-by: NRob Herring <rob.herring@calxeda.com> Reviewed-by: NTom Rini <trini@ti.com>
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由 Rob Herring 提交于
gcc 4.7 will generate unaligned accesses to local char arrays, so make them static to avoid that. Signed-off-by: NRob Herring <rob.herring@calxeda.com> Reviewed-by: NTom Rini <trini@ti.com>
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由 Richard Gibbs 提交于
The AHCI driver was incorrectly using the Capabilities register NP (number of ports) field to determine which ports to activate. This commit changes it to correctly use the PORTS_IMPL register as a port map. Signed-off-by: NRichard Gibbs <richard.gibbs@calxeda.com> Reviewed-by: NTom Rini <trini@ti.com>
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