Use CONFIG_TARGET_P4080DS instead.
Signed-off-by: NYork Sun <york.sun@nxp.com>

Replace CONFIG_PPC_P4080 with ARCH_P4080 in Kconfig and clean up
existing macros.
Signed-off-by: NYork Sun <york.sun@nxp.com>

We need to ensure that CONFIG_PHYS_64BIT is configured via Kconfig so
that it is always available to the build system.  Otherwise we can run
into cases where we have inconsistent sizes of certain attributes.

Ravi Babu reported offset mismatch of struct dwc3 across files since
commit 95ebc253 ("types.h: move and redefine resource_size_t").
Since the commit, resource_addr_t points to phys_addr_t, whose size
is dependent on CONFIG_PHYS_64BIT for ARM architecture.

I tried my best to use "select" where possible (for example, ARMv8
architecture) because I think this kind of option is generally user-
unconfigurable.  However, I see some of PowerPC boards have 36BIT
defconfigs as well as 32BIT ones.  I moved CONFIG_PHYS_64BIT to the
defconfigs for such boards.

CONFIG_36BIT is no longer referenced, so all of the defines were
removed from CONFIG_SYS_EXTRA_OPTIONS.

Fixes: 95ebc253 ("types.h: move and redefine resource_size_t")
Signed-off-by: NMasahiro Yamada <yamada.masahiro@socionext.com>
Reported-by: NRavi Babu <ravibabu@ti.com>
Acked-by: NStefan Roese <sr@denx.de>
Reviewed-by: NTom Rini <trini@konsulko.com>
Reviewed-by: NYork Sun <york.sun@nxp.com>

Signed-off-by: NShaohui Xie <Shaohui.Xie@freescale.com>
Acked-by: NYork Sun <yorksun@freescale.com>

Signed-off-by: NWolfgang Denk <wd@denx.de>
[trini: Fixup common/cmd_io.c]
Signed-off-by: NTom Rini <trini@ti.com>

Currently, the macro "CONFIG_SYS_FSL_SRIO_PCIE_BOOT_MASTER" can enable
the master module of Boot from SRIO and PCIE on a platform. But this
is not a silicon feature, it's just a specific booting mode based on
the SRIO and PCIE interfaces. So it's inappropriate to put the macro
into the file arch/powerpc/include/asm/config_mpc85xx.h.

Change the macro "CONFIG_SYS_FSL_SRIO_PCIE_BOOT_MASTER" to
"CONFIG_SRIO_PCIE_BOOT_MASTER", remove them from
arch/powerpc/include/asm/config_mpc85xx.h file, and add those macros
in configuration header file of each board which can support the
master module of Boot from SRIO and PCIE.
Signed-off-by: NLiu Gang <Gang.Liu@freescale.com>
Signed-off-by: NAndy Fleming <afleming@freescale.com>

The P5040 does not have SRIO, so don't put the SRIO definitions in
corenet_ds.h.  They belong in the board-specific header files.
Signed-off-by: NTimur Tabi <timur@freescale.com>
Signed-off-by: NAndy Fleming <afleming@freescale.com>

These are not supported as individual build targets, but instead
are supported by another target.

The dead p4040 defines in particular had bitrotted significantly.
Signed-off-by: NScott Wood <scottwood@freescale.com>
Acked-by: NKumar Gala <galak@kernel.crashing.org>
Signed-off-by: NAndy Fleming <afleming@freescale.com>

Move some SoC/board specific defines out of corenet_ds.h and into the
corresponding P3041DS/P4080DS/P5020.h.

We moved CONFIG_MMC, CONFIG_PCIE3, & CONFIG_FSL_NGPIXIS because the P3060
SoC/reference board does not have these devices and it will share the same
board code.
Signed-off-by: NKumar Gala <galak@kernel.crashing.org>

Add new headers that capture common defines for a given SoC/processor
rather than duplicating that information in board config.h and random
other places.

Eventually this should be handled by Kconfig & defconfigs
Signed-off-by: NKumar Gala <galak@kernel.crashing.org>
Acked-by: NWolfgang Denk <wd@denx.de>

Simultaneous FCM and GPCM or UPM operation may erroneously trigger bus
monitor timeout.  Set timeout to maximum to avoid.

Based on a patch from Lan Chunhe <b25806@freescale.com>
Signed-off-by: NKumar Gala <galak@kernel.crashing.org>

CoreNet Platform Cache single-bit data error scrubbing will cause data
corruption.  Disable the feature to workaround the issue.
Signed-off-by: NKumar Gala <galak@kernel.crashing.org>

CoreNet Platform Cache single-bit tag error scrubbing will cause tag
corruption.  Disable the feature to workaround the issue.
Signed-off-by: NKumar Gala <galak@kernel.crashing.org>

False multi-bit ECC errors will be reported by the eSDHC buffer which
can trigger a reset request.

We disable all ECC error checking on SDHC.
Signed-off-by: NRoy Zang <tie-fei.zang@freescale.com>
Signed-off-by: NKumar Gala <galak@kernel.crashing.org>

The default value of the SRS, VS18 and VS30 and ADMAS fields in the host
controller capabilities register (HOSTCAPBLT) are incorrect. The default
of these bits should be zero instead of one.

Clear these bits out when we read HOSTCAPBLT.
Signed-off-by: NRoy Zang <tie-fei.zang@freescale.com>
Signed-off-by: NKumar Gala <galak@kernel.crashing.org>

Do not issue a manual asynchronous CMD12. Instead, use a (software)
synchronous CMD12 or AUTOCMD12 to abort data transfer.
Signed-off-by: NJerry Huang <Chang-Ming.Huang@freescale.com>
Signed-off-by: NRoy Zang <tie-fei.zang@freescale.com>
Signed-off-by: NKumar Gala <galak@kernel.crashing.org>

We appear to have different refclk's on the different corenet DS boards
so move the define out of the common header.
Signed-off-by: NKumar Gala <galak@kernel.crashing.org>

CONFIG_SYS_TEXT_BASE setting is common across the 'corenet_ds' board
family so move it out of P4080DS.h and into corenet_ds.h
Signed-off-by: NKumar Gala <galak@kernel.crashing.org>

Clean up Makefile, and drop a lot of the config.mk files on the way.

We now also automatically pick all boards that are listed in
boards.cfg (and with all configurations), so we can drop the redundant
entries from MAKEALL to avoid building these twice.
Signed-off-by: NWolfgang Denk <wd@denx.de>

Add support for the P4080DS board, with the following features:

* 36-bit only
* Boots from NOR flash
* FMAN drivers NOT supported
* SPD DDR initialization
Signed-off-by: NEd Swarthout <Ed.Swarthout@freescale.com>
Signed-off-by: NEmil Medve <Emilian.Medve@Freescale.com>
Signed-off-by: NBecky Bruce <beckyb@kernel.crashing.org>
Signed-off-by: NAshish Kalra <Ashish.Kalra@freescale.com>
Signed-off-by: NStuart Yoder <stuart.yoder@freescale.com>
Signed-off-by: NDave Liu <daveliu@freescale.com>
Signed-off-by: NLan Chunhe-B25806 <b25806@freescale.com>
Signed-off-by: NScott Wood <scottwood@freescale.com>
Signed-off-by: NKim Phillips <kim.phillips@freescale.com>
Signed-off-by: NRoy Zang <tie-fei.zang@freescale.com>
Signed-off-by: NTimur Tabi <timur@freescale.com>
Signed-off-by: NAndy Fleming <afleming@freescale.com>
Signed-off-by: NYork Sun <yorksun@freescale.com>
Signed-off-by: NKumar Gala <galak@kernel.crashing.org>

This helps to clean up the include/ directory so that it only contains
non-architecture-specific headers and also matches Linux's directory
layout which many U-Boot developers are already familiar with.
Signed-off-by: NPeter Tyser <ptyser@xes-inc.com>

* prepare joining at91 and at91rm9200
 * add modified copy of soc files to cpu/arm920t/at91 to make
   possible to compile at91rm9200 boards in at91 tree instead
   of at91rm9200
 * add header files with c structure defs for AT91 MC, ST and TC
 * the new cpu files are using at91 c structure soc access
 * please read README.soc-at91 for details
Signed-off-by: NJens Scharsig <js_at_ng@scharsoft.de>

Xilinx ppc440 and ppc405 have many similarities. This patch merge the
config files of both infrastuctures
Signed-off-by: NRicardo Ribalda Delgado <ricardo.ribalda@uam.es>
Signed-off-by: NStefan Roese <sr@denx.de>

As "ppc44x: Unification of virtex5 pp440 boards" did for the xilinx
ppc440 boards, this patch presents a common architecture for all the
xilinx ppc405 boards.

Any custom xilinx ppc405 board can be added very easily with no code
duplicity.

This patch also adds a simple generic board, that can be used on almost
any design with xilinx ppc405 replacing the file ppc405-generic/xparameters.h

This patch is prepared to work with the latest version of EDK (10.1)
Signed-off-by: NRicardo Ribalda Delgado <ricardo.ribalda@uam.es>
Signed-off-by: NStefan Roese <sr@denx.de>