1. 11 6月, 2019 16 次提交
  2. 06 6月, 2019 3 次提交
  3. 05 6月, 2019 1 次提交
  4. 04 6月, 2019 1 次提交
  5. 31 5月, 2019 2 次提交
  6. 30 5月, 2019 3 次提交
  7. 24 5月, 2019 1 次提交
  8. 23 5月, 2019 2 次提交
    • P
      ARM: dts: stm32mp1: DDR config v1.44 · 067a4c00
      Patrick Delaunay 提交于
      Update DDR configuration with the latest update:
      
      - PUBL_regs: DXnGCR[0]= according to ddr_width to disable Byte
                              lane 2/3 in 16bit
      - fix LPDDR2/3 timing_calc to step RL/WL in relaxed
        timings mode
      - remove  LPDDR3 RL3 (optional) support vs  MR0[7]
        because MR0[7] can't be read instead  always apply
        worse RL/WL for LPDDR3 when freq < 166MHz)
      - change  MR3 to 48ohm drive  for LPDDR2/3
      - change default ZPROG[7:4] = 0x1 for LPDDR2/3 ,
        '0' is not allowed even when ODT not used
      - use DQSTRN for LPDDR2/3 (it was not set in PIR)
      - LPDDR3: set dqsge/dwsgx gate extension to 2,2
        like LPDDR2
      -DDRCTRL.dfitmg0:
        + for LPDDR3 tphy_wrlat = WL (as LPDDR2)
        + improvement for relaxed mode vs  RL/Wl at corner case.
          For example @533MHz RL/WL (relaxed) = 9/5 for LPDDR2/3
          and correction to MR2 accordingly
      - DDR_PCFGQOS1_1: port1 timeout relaxed from 0x00 to 0x40,
        for LTDC.
      - DDR_PCFGWQOS0_0: change vpr level from
        11 to 12 in order to include the CPU on
        the variable priority queue.
      - DDR_SCHED: fix to consider 13 levels  (13 levels - 1 = 0xC)
      Signed-off-by: NPatrick Delaunay <patrick.delaunay@st.com>
      067a4c00
    • P
      stm32mp1: ram: change ddr speed to kHz · c60fed14
      Patrick Delaunay 提交于
      Allow fractional support in DDR tools.
      Signed-off-by: NPatrick Delaunay <patrick.delaunay@st.com>
      c60fed14
  9. 22 5月, 2019 6 次提交
  10. 20 5月, 2019 3 次提交
    • P
      imx: mx6sabresd: fix boot hang with video · 9002e735
      Peng Fan 提交于
      Meet the following boot hang.
      "
      U-Boot SPL 2019.04-00661-gdc80a012e4 (Apr 25 2019 - 10:31:57 +0800)
      Trying to boot from MMC1
      
      U-Boot 2019.04-00661-gdc80a012e4 (Apr 25 2019 - 10:31:57 +0800)
      
      CPU:   Freescale i.MX6Q rev1.5 996 MHz (running at 792 MHz)
      CPU:   Automotive temperature grade (-40C to 125C)Reset cause: POR
      Model: Freescale i.MX6 Quad SABRE Smart Device Board
      Board: MX6-SabreSD
      I2C:   ready
      DRAM:  1 GiB
      Video device 'ipu@2400000' cannot allocate frame buffer memory -ensure the device is set up before relocation
      Error binding driver 'ipuv3_video': -28
      Video device 'ipu@2800000' cannot allocate frame buffer memory -ensure the device is set up before relocation
      Error binding driver 'ipuv3_video': -28
      Some drivers failed to bind
      Error binding driver 'generic_simple_bus': -28
      Some drivers failed to bind
      initcall sequence 4ffe4500 failed at call 1780dfb7 (err=-28)
      "
      
      1. fdtdec_get_alias_seq will use "video" as base, however in alias node,
         we use ipux, so add new alias for U-Boot dts.
      2. DM_VIDEO is enabled, however reserve_video is called before
         relocation, so to make DM_VIDEO work before relocation, need to
         set SYS_MALLOC_F_LEN
      3. defconfig is updated with savedefconfig
      
       Note: I do not have a video panel to test, but with this patch, U-Boot
             boots up again, below log.
      
      "
      U-Boot SPL 2019.04-00662-g0b62453bff (Apr 25 2019 - 10:36:31 +0800)
      Trying to boot from MMC1
      
      U-Boot 2019.04-00662-g0b62453bff (Apr 25 2019 - 10:36:31 +0800)
      
      CPU:   Freescale i.MX6Q rev1.5 996 MHz (running at 792 MHz)
      CPU:   Automotive temperature grade (-40C to 125C) at 34C
      Reset cause: POR
      Model: Freescale i.MX6 Quad SABRE Smart Device Board
      Board: MX6-SabreSD
      I2C:   ready
      DRAM:  1 GiB
      PMIC:  PFUZE100 ID=0x10
      MMC:   FSL_SDHC: 0, FSL_SDHC: 1, FSL_SDHC: 3
      Loading Environment from MMC... *** Warning - bad CRC, using default environment
      
      PCI:   pcie phy link never came up
      In:    serial
      Out:   serial
      Err:   serial
      Net:   FEC [PRIME]
      Hit any key to stop autoboot:  0
      "
      Signed-off-by: NPeng Fan <peng.fan@nxp.com>
      Reviewed-by: NAnatolij Gustschin <agust@denx.de>
      9002e735
    • S
      arm: imx: add ipu to imx53.dts and set dm-pre-reloc · c11599b4
      Steffen Dirkwinkel 提交于
      The ipu node in imx53 is needed for DM_VIDEO. We also need to set
      u-boot,dm-pre-reloc to initialize before relocation.
      Signed-off-by: NSteffen Dirkwinkel <s.dirkwinkel@beckhoff.com>
      c11599b4
    • S
      arm: mvebu: armada-370-xp.dtsi: Add "u-boot, dm-pre-reloc" to "internal-regs" · 1718a9f3
      Stefan Roese 提交于
      Without this U-Boot specific property, booting on Armada XP theadorable
      fails in SPL. All nodes in the "internal-regs" (simple-bus) DT node are
      not scanned, so the UART node is missing (and others).
      
      I'm not adding this property in an *u-boot.dtsi file, since there is
      none matching the generic rules for all files including this dtsi
      file. So to not miss any of the boards using this dtsi file, I'm
      adding it to this file directly, which makes the Linux merge a less
      easy unforunately.
      Signed-off-by: NStefan Roese <sr@denx.de>
      Cc: Chris Packham <judge.packham@gmail.com>
      Cc: Marek Behún <marek.behun@nic.cz>
      Reviewed-by: NChris Packham <judge.packham@gmail.com>
      1718a9f3
  11. 19 5月, 2019 2 次提交