1. 01 1月, 2019 1 次提交
  2. 14 12月, 2018 1 次提交
  3. 03 12月, 2018 2 次提交
  4. 16 10月, 2018 1 次提交
    • M
      arm64: versal: Add support for new Xilinx Versal ACAPs · ec48b6c9
      Michal Simek 提交于
      Xilinx is introducing Versal, an adaptive compute acceleration platform
      (ACAP), built on 7nm FinFET process technology. Versal ACAPs combine
      Scalar Processing Engines, Adaptable Hardware Engines, and Intelligent
      Engines with leading-edge memory and interfacing technologies to deliver
      powerful heterogeneous acceleration for any application. The Versal AI
      Core series has five devices, offering 128 to 400 AI Engines. The series
      includes dual-core Arm Cortex™-A72 application processors, dual-core Arm
      Cortex-R5 real-time processors, 256KB of on-chip memory with ECC, more
      than 1,900 DSP engines optimized for high-precision floating point with
      low latency.
      
      The patch is adding necessary infrastructure in place without enabling
      platform which is done in separate patch.
      Signed-off-by: NMichal Simek <michal.simek@xilinx.com>
      ec48b6c9
  5. 11 9月, 2018 1 次提交
  6. 17 8月, 2018 1 次提交
  7. 06 8月, 2018 1 次提交
  8. 04 8月, 2018 1 次提交
  9. 30 7月, 2018 1 次提交
  10. 11 7月, 2018 1 次提交
    • T
      vboot: Add FIT_SIGNATURE_MAX_SIZE protection · 72239fc8
      Teddy Reed 提交于
      This adds a new config value FIT_SIGNATURE_MAX_SIZE, which controls the
      max size of a FIT header's totalsize field. The field is checked before
      signature checks are applied to protect from reading past the intended
      FIT regions.
      
      This field is not part of the vboot signature so it should be sanity
      checked. If the field is corrupted then the structure or string region
      reads may have unintended behavior, such as reading from device memory.
      A default value of 256MB is set and intended to support most max storage
      sizes.
      Suggested-by: NSimon Glass <sjg@chromium.org>
      Signed-off-by: NTeddy Reed <teddy.reed@gmail.com>
      Reviewed-by: NSimon Glass <sjg@chromium.org>
      72239fc8
  11. 24 5月, 2018 2 次提交
    • M
      spl: Add full fitImage support · 8a9dc16e
      Marek Vasut 提交于
      Add support for loading U-Boot and optionally FDT from a fitImage
      in SPL by using the full fitImage support from U-Boot. While we do
      have limited SPL loading support in SPL with a small footprint, it
      is missing a lot of important features, like checking signatures.
      This support has all the fitImage features, while the footprint is
      obviously larger.
      Signed-off-by: NMarek Vasut <marex@denx.de>
      Cc: Pantelis Antoniou <pantelis.antoniou@konsulko.com>
      Cc: Simon Glass <sjg@chromium.org>
      Reviewed-by: NSimon Glass <sjg@chromium.org>
      8a9dc16e
    • M
      fit: Fix CONFIG_FIT_SPL_PRINT · b527b9c6
      Marek Vasut 提交于
      Rename CONFIG_FIT_SPL_PRINT to CONFIG_SPL_FIT_PRINT and add Kconfig
      entry for it.
      Signed-off-by: NMarek Vasut <marex@denx.de>
      Cc: Pantelis Antoniou <pantelis.antoniou@konsulko.com>
      Cc: Simon Glass <sjg@chromium.org>
      Reviewed-by: NSimon Glass <sjg@chromium.org>
      b527b9c6
  12. 07 5月, 2018 1 次提交
  13. 28 4月, 2018 3 次提交
  14. 17 4月, 2018 1 次提交
    • S
      Kconfig: Enlarge default SYS_MALLOC_F_LEN for AM33XX · 90e407ae
      Sjoerd Simons 提交于
      Since commit 8e14ba7b ("gpio: omap_gpio: Add DM_FLAG_PRE_RELOC
      flag") omap GPIO gets bound before relocation.  Unfortunately due to
      this, on at least the beaglebone black, the pre-relocation memory pool
      gets exhausted before probing the serial port. This then causes u-boot
      to panic as CONFIG_REQUIRE_SERIAL_CONSOLE is set...
      
      Resolve this by resizing the default size of the pre-relocation malloc
      pool for AM335X platforms.
      Signed-off-by: NSjoerd Simons <sjoerd.simons@collabora.co.uk>
      90e407ae
  15. 14 4月, 2018 4 次提交
  16. 14 3月, 2018 1 次提交
  17. 28 2月, 2018 1 次提交
  18. 24 2月, 2018 1 次提交
  19. 23 2月, 2018 1 次提交
  20. 11 2月, 2018 1 次提交
    • T
      configs: Migrate CONFIG_SYS_TEXT_BASE · 278b90ce
      Tom Rini 提交于
      On the NIOS2 and Xtensa architectures, we do not have
      CONFIG_SYS_TEXT_BASE set.  This is a strict migration of the current
      values into the defconfig and removing them from the headers.
      
      I did not attempt to add more default values in and for now will leave
      that to maintainers.
      Signed-off-by: NTom Rini <trini@konsulko.com>
      278b90ce
  21. 09 2月, 2018 1 次提交
  22. 31 1月, 2018 1 次提交
  23. 18 11月, 2017 1 次提交
  24. 24 10月, 2017 1 次提交
  25. 19 10月, 2017 1 次提交
    • H
      x86: provide CONFIG_BUILD_ROM · 871aa41d
      Heinrich Schuchardt 提交于
      Up to now we depended on an exported variable to build u-boot.rom.
      We should be able to specify it in the configuration file, too.
      
      With this patch this becomes possible using the new Kconfig option
      CONFIG_BUILD_ROM.
      
      This option depends on CONFIG_X86 and is selected in
      qemu-x86_defconfig and qemu-x86_64_defconfig.
      
      Cc: Simon Glass <sjg@chromium.org>
      Cc: Bin Meng <bmeng.cn@gmail.com>
      Signed-off-by: NHeinrich Schuchardt <xypron.glpk@gmx.de>
      Reviewed-by: NBin Meng <bmeng.cn@gmail.com>
      871aa41d
  26. 16 10月, 2017 1 次提交
  27. 09 10月, 2017 1 次提交
  28. 02 9月, 2017 1 次提交
  29. 15 8月, 2017 1 次提交
  30. 13 8月, 2017 1 次提交
  31. 05 8月, 2017 1 次提交
  32. 27 7月, 2017 1 次提交
  33. 22 5月, 2017 1 次提交
    • T
      lib: move hash CONFIG options to Kconfig · 089df18b
      Tom Rini 提交于
      Commit 94e3c8c4 ("crypto/fsl - Add progressive hashing support
      using hardware acceleration.") created entries for CONFIG_SHA1,
      CONFIG_SHA256, CONFIG_SHA_HW_ACCEL, and CONFIG_SHA_PROG_HW_ACCEL.
      However, no defconfig has migrated to it.  Complete the move by first
      adding additional logic to various Kconfig files to select this when
      required and then use the moveconfig tool.  In many cases we can select
      these because they are required to implement other drivers.  We also
      correct how we include the various hashing algorithms in SPL.
      
      This commit was generated as follows (after Kconfig additions):
      
      [1] tools/moveconfig.py -y SHA1 SHA256 SHA_HW_ACCEL
      [2] tools/moveconfig.py -y SHA_PROG_HW_ACCEL
      
      Note:
      We cannot move SHA_HW_ACCEL and SHA_PROG_HW_ACCEL simultaneously
      because there is dependency between them.
      
      Cc: Poonam Aggrwal <poonam.aggrwal@freescale.com>
      Cc: Naveen Burmi <NaveenBurmi@freescale.com>
      Cc: Po Liu <po.liu@freescale.com>
      Cc: Shengzhou Liu <Shengzhou.Liu@freescale.com>
      Cc: Priyanka Jain <Priyanka.Jain@freescale.com>
      Cc: Shaohui Xie <Shaohui.Xie@freescale.com>
      Cc: Chunhe Lan <Chunhe.Lan@freescale.com>
      Cc: Chander Kashyap <k.chander@samsung.com>
      Cc: Steve Rae <steve.rae@raedomain.com>
      Cc: Dirk Eibach <eibach@gdsys.de>
      Cc: Feng Li <feng.li_2@nxp.com>
      Cc: Alison Wang <alison.wang@freescale.com>
      Cc: Sumit Garg <sumit.garg@nxp.com>
      Cc: Mingkai Hu <Mingkai.Hu@freescale.com>
      Cc: York Sun <york.sun@nxp.com>
      Cc: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
      Cc: Jaehoon Chung <jh80.chung@samsung.com>
      Cc: Akshay Saraswat <akshay.s@samsung.com>
      Cc: Heiko Schocher <hs@denx.de>
      Cc: Jagan Teki <jagan@amarulasolutions.com>
      Signed-off-by: NTom Rini <trini@konsulko.com>
      Reviewed-by: NSimon Glass <sjg@chromium.org>
      Signed-off-by: NTom Rini <trini@konsulko.com>
      089df18b