- 10 12月, 2019 1 次提交
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由 Lukas Auer 提交于
Add the function riscv_get_ipi() for reading the pending status of IPIs. The supported controllers are Andes' Platform Level Interrupt Controller (PLIC), the Supervisor Binary Interface (SBI), and SiFive's Core Local Interruptor (CLINT). Signed-off-by: NLukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: NRick Chen <rick@andestech.com>
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- 08 4月, 2019 1 次提交
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由 Lukas Auer 提交于
The supervisor binary interface (SBI) provides the necessary functions to implement the platform IPI functions riscv_send_ipi() and riscv_clear_ipi(). Use it to implement them. This adds support for inter-processor interrupts (IPIs) on RISC-V CPUs running in supervisor mode. Support for machine mode is already available for CPUs that include the SiFive CLINT. Signed-off-by: NLukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: NAnup Patel <anup.patel@wdc.com> Reviewed-by: NBin Meng <bmeng.cn@gmail.com> Reviewed-by: NAtish Patra <atish.patra@wdc.com> Tested-by: NBin Meng <bmeng.cn@gmail.com>
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