When CONFIG_DMA is defined the default spi_flash_copy_mmap() can
handle dma memory copy, so compile out spi_flash_copy_mmap() from
ti_qspi driver when CONFIG_DMA config is defined.
Signed-off-by: NMugunthan V N <mugunthanvnm@ti.com>
Reviewed-by: NSimon Glass <sjg@chromium.org>
Reviewed-by: NJagan Teki <jteki@openedev.com>

Add dma memcpy api to the default spi_flash_copy_mmap(), so that
dma will be used to copy data when CONFIG_DMA is defined for the
platform.
Signed-off-by: NMugunthan V N <mugunthanvnm@ti.com>
Reviewed-by: NSimon Glass <sjg@chromium.org>
Reviewed-by: NJagan Teki <jteki@openedev.com>

Add TI_EDMA3 entry on Kconfig with help description.
Signed-off-by: NMugunthan V N <mugunthanvnm@ti.com>
Reviewed-by: NSimon Glass <sjg@chromium.org>
Reviewed-by: NJagan Teki <jteki@openedev.com>

Implement a DMA uclass so that the devices like ethernet, spi,
mmc etc can offload the data transfers from/to the device and
memory.
Signed-off-by: NMugunthan V N <mugunthanvnm@ti.com>
Reviewed-by: NSimon Glass <sjg@chromium.org>
Reviewed-by: NJagan Teki <jteki@openedev.com>

Extend options for saving variables to QSPI.
Reviewed-by: NJagan Teki <jteki@openedev.com>
Signed-off-by: NMichal Simek <monstr@monstr.eu>

In current design, if any peripheral was assigned to both A7 and M4,
it will receive ipg_stop or ipg_wait when any of the 2 platforms
enter low power mode. We will have a risk that, if A7 enter wait,
M4 enter stop, peripheral will have chance to get ipg_stop and ipg_wait
asserted same time. Also if M4 enters stop mode, A7 will have no
chance to access the peripheral.
There are 26 peripherals affected by this IC issue:
SIM2(sim2/emvsim2)
SIM1(sim1/emvsim1)
UART1/UART2/UART3/UART4/UART5/UART6/UART7
SAI1/SAI2/SAI3
WDOG1/WDOG2/WDOG3/WDOG4
GPT1/GPT2/GPT3/GPT4
PWM1/PWM2/PWM3/PWM4
ENET1/ENET2
Software Workaround:
The solution is to set the peripherals to Domain0 by A core, since A core
in Domain0. The peripherals which will be used by M4, will be set to Domain1
by M4.
For example, A core set WDOG4 to domain0, but when M4 boots up, M4 will
set WDOG4 to domain1, because M4 will use WDOG4.

So the peripherals are not shared by them. This way requires
the uboot implemented the RDC driver and set the 26 IPs above
to domain 0 only. M4 image will set the M4 to domain 1 and
set peripheral which it will use to domain 1.

This patch enables the CONFIG_IMX_RDC and CONFIG_IMX_BOOTAUX for
i.MX7D SABRESD board, and setup the 26 IP resources to domain 0.
Signed-off-by: NYe.Li <ye.li@nxp.com>
Signed-off-by: NPeng Fan <peng.fan@nxp.com>

Introduce macros and command to support booting M4 core for
i.MX7D SabreSD board.
Signed-off-by: NYe.Li <ye.li@nxp.com>
Signed-off-by: NPeng Fan <peng.fan@nxp.com>

Implement arch_auxiliary_core_up and arch_auxiliary_core_check_up.

arch_auxiliary_core_check_up is used to check whether M4 is running
or not. arch_auxiliary_core_up is to boot M4 core, the m4 core will
use the pc and stack which is set in arch_auxiliary_core_up to set R15
and R13 register and boot.
Signed-off-by: NYe.Li <ye.li@nxp.com>
Signed-off-by: NPeng Fan <peng.fan@nxp.com>

Introduce macros and command to support booting M4 core for
i.MX6SX SabreSD board.
Signed-off-by: NYe.Li <ye.li@nxp.com>
Signed-off-by: NPeng Fan <peng.fan@nxp.com>

Implement arch_auxiliary_core_up and arch_auxiliary_core_check_up.

arch_auxiliary_core_check_up is used to check whether M4 is running
or not. arch_auxiliary_core_up is to boot M4 core, the m4 core will
use the pc and stack which is set in arch_auxiliary_core_up to set R15
and R13 register and boot.
Signed-off-by: NYe.Li <ye.li@nxp.com>
Signed-off-by: NPeng Fan <peng.fan@nxp.com>

To boot a auxiliary core in asymmetric multicore system, introduce the
new command "bootaux" to do it. Example of boot auxliary core from
0x70000000 where stores the boot head information that should be
parsed by auxiliary core, "bootaux 0x70000000".
Introduce Kconfig option IMX_BOOTAUX.
Signed-off-by: NYe.Li <ye.li@nxp.com>
Signed-off-by: NPeng Fan <peng.fan@nxp.com>

If CONFIG_IMX_RDC is enabled, enable clock for RDC and SEMAPHORE.
Signed-off-by: NPeng Fan <peng.fan@nxp.com>

Add the peripherals/masters definitions and registers base addresses
for mx7d RDC.
Signed-off-by: NYe.Li <ye.li@nxp.com>
Signed-off-by: NPeng Fan <peng.fan@nxp.com>

Add the definitions for the RDC mappings for i.MX6 SoloX.
Signed-off-by: NYe.Li <ye.li@nxp.com>
Signed-off-by: NPeng Fan <peng.fan@nxp.com>

Introduce Resource Domain Controller support for i.MX.
Now i.MX6SX and i.MX7D supports this feature to assign masters
and peripherals to different domains.
Signed-off-by: NYe.Li <ye.li@nxp.com>
Signed-off-by: NPeng Fan <peng.fan@nxp.com>

Introudce rdc regs structure and rdc sema reg structure for i.MX6.
For now, to i.MX6, only i.MX6SX supports this.
Signed-off-by: NYe.Li <ye.li@nxp.com>
Signed-off-by: NPeng Fan <peng.fan@nxp.com>

Add board_mmc_getcd function and declare CD_GPIO for SDCard.
Signed-off-by: NJulien Corjon <corjon.j@ecagroup.com>

Specify max_bus_width directly in usdhc_cfg static definition instead
of tweaking it in the board_mmc_init() function.
Signed-off-by: NJulien Corjon <corjon.j@ecagroup.com>

USDHC2 does not exist on mx6quq7 board, as USDHC4 was already been
declared this is probably a typo.
Signed-off-by: NJulien Corjon <corjon.j@ecagroup.com>
Acked-by: NBoris Brezillon <boris.brezillon@free-electrons.com>

Implement board specific functions to select the environment device and
partition when booting from SD/MMC.

SD2:  mmc 0 0
SD3:  mmc 1 0
eMMC: mmc 2 1
Signed-off-by: NSoeren Moch <smoch@web.de>

commit 216d286c [imx: mx6: implement
mmc_get_env_dev] introduced selection of the environment device according
to the boot device when booting from SD/MMC.

Extend this functionality for also selecting the device partition.
Signed-off-by: NSoeren Moch <smoch@web.de>

Introudce i.MX7 pinctrl driver support.
For now only i.MX7D supported.
There are two iomux controllers in i.MX7D, iomuxc and iomuxc_lpsr.
To iomuxc_lpsr, ZERO_OFFSET_VALID is set, means offset of mux_reg
and conf_reg can begin at 0.
Signed-off-by: NPeng Fan <van.freenix@gmail.com>
Reviewed-by: NSimon Glass <sjg@chromium.org>

Introduce pinctrl for i.MX6
1. pinctrl-imx.c is for common usage. It's used by i.MX6/7.
2. Add PINCTRL_IMX PINCTRL_IMX6 Kconfig entry.
3. To the pinctrl_ops implementation, only set_state is implemented.
   To i.MX6/7, the pinctrl dts entry is as following:
&iomuxc {
        pinctrl-names = "default";

        pinctrl_csi1: csi1grp {
                fsl,pins = <
                MX6UL_PAD_CSI_MCLK__CSI_MCLK            0x1b088
                MX6UL_PAD_CSI_PIXCLK__CSI_PIXCLK        0x1b088
                MX6UL_PAD_CSI_VSYNC__CSI_VSYNC          0x1b088
                >;
        };

        [.....]
};
  there is no property named function or groups. So pinctrl_generic_set_state
  can not be used here.
5. This driver is a simple implementation for i.mx iomux controller,
   only parse the fsl,pins property and write value to registers.
6. With DEBUG enabled, we can see log when "i2c bus 0":
   "
   set_state_simple op missing
   imx_pinctrl_set_state: i2c1grp
   mux_reg 0x14c, conf_reg 0x3bc, input_reg 0x5d8, mux_mode 0x0, input_val 0x1, config_val 0x4000007f
   write mux: offset 0x14c val 0x10
   select_input: offset 0x5d8 val 0x1
   write config: offset 0x3bc val 0x7f
   mux_reg 0x148, conf_reg 0x3b8, input_reg 0x5d4, mux_mode 0x0, input_val 0x1, config_val 0x4000007f
   write mux: offset 0x148 val 0x10
   select_input: offset 0x5d4 val 0x1
   write config: offset 0x3b8 val 0x7f
   "
   this means imx6 pinctrl driver works as expected.
Signed-off-by: NPeng Fan <van.freenix@gmail.com>
Reviewed-by: NSimon Glass <sjg@chromium.org>

Refactored data structure for CAAM's job ring and Secure Memory
to support i.MX7.

The new memory map use macros to resolve SM's offset by version.
This will solve the versioning issue caused by the new version of
secure memory of i.MX7
Signed-off-by: NUlises Cardenas <raul.casas@nxp.com>
Reviewed-by: NStefano Babic <sbabic@denx.de>

When running the 'ums' command we get:

=> ums 0 mmc 0
UMS: disk start sector: 0x0, count: 0xe18000
g_dnl_register: failed!, error: -22
ERROR: g_dnl_register failed
at common/cmd_usb_mass_storage.c:107/do_usb_mass_storage()

Fix this by initializing USB OTG1 port as USB device mode instead of host.
Signed-off-by: NFabio Estevam <fabio.estevam@nxp.com>

Use the new NXP email address for the board maintainer.
Signed-off-by: NFabio Estevam <fabio.estevam@nxp.com>

Select CONFIG_FSL_QSPI so that the SPI can be probed:

=> sf probe
SF: Detected N25Q256 with page size 256 Bytes, erase size 64 KiB, total 32 MiB
Signed-off-by: NFabio Estevam <fabio.estevam@nxp.com>
Reviewed-by: NPeng Fan <peng.fan@nxp.com>

Commit 276d3ebb removed htole32() but missed
to remove the corresponding header. This is annoying, since BSD systems do not
have endian.h.
Signed-off-by: NAndreas Bießmann <andreas.devel@googlemail.com>
Acked-by: NMarek Vasut <marex@denx.de>
Acked-by: NMichael Heimpold <mhei@heimpold.de>

Update existing documentation to mention Intel Bayley Bay board
instructions, an additional Bay Trail based board to MinnowMax.

This also adds a minor change to QEMU section to indicate clearly
the instructions are for bare mode.
Signed-off-by: NBin Meng <bmeng.cn@gmail.com>
Reviewed-by: NSimon Glass <sjg@chromium.org>

This adds basic support to Intel Cougar Canyon 2 board, a board
based on Chief River platform with an Ivy Bridge processor and
a Panther Point chipset.
Signed-off-by: NBin Meng <bmeng.cn@gmail.com>
Acked-by: NSimon Glass <sjg@chromium.org>

Wrap initialization codes with #ifndef CONFIG_HAVE_FSP #endif,
and enable the build for both FSP and non-FSP configurations.
Signed-off-by: NBin Meng <bmeng.cn@gmail.com>
Reviewed-by: NSimon Glass <sjg@chromium.org>

Intel IvyBridge FSP seems to be buggy that it does not report memory
used by FSP itself as reserved in the resource descriptor HOB. The
FSP specification does not describe how resource descriptor HOBs are
generated by the FSP to describe what memory regions. It looks newer
FSPs like Queensbay and BayTrail do not have such issue. This causes
U-Boot relocation overwrites the important boot service data which is
used by FSP, and the subsequent call to fsp_notify() will fail.

To resolve this, we find out the lowest memory base address allocated
by FSP for the boot service data when walking through the HOB list in
fsp_get_usable_lowmem_top(). Check whether the memory top address is
below the FSP HOB list, and if not, use the lowest memory base address
allocated by FSP as the memory top address.
Signed-off-by: NBin Meng <bmeng.cn@gmail.com>
Acked-by: NSimon Glass <sjg@chromium.org>
Tested on link (ivybridge non-FSP)
Tested-by: NSimon Glass <sjg@chromium.org>

The SMSC SIO1007 superio chipset integrates two ns16550 compatible
serial ports for legacy applications, 16 GPIO pins and some other
functionalities like power management.

This adds a simple driver to enable serial port and handle GPIO.
Signed-off-by: NBin Meng <bmeng.cn@gmail.com>
Reviewed-by: NSimon Glass <sjg@chromium.org>

IvyBridge FSP package is built with a base address at 0xfff80000,
and does not use UPD data region. This adds basic FSP support.
Signed-off-by: NBin Meng <bmeng.cn@gmail.com>
Acked-by: NSimon Glass <sjg@chromium.org>
Tested on link (ivybridge non-FSP)
Tested-by: NSimon Glass <sjg@chromium.org>

Purely by code inspection, it looks like the parameter order to memalign()
is swapped; its parameters are (align, size). 4096 is a likely desired
alignment, and a variable named size sounds like a size:-)

Fixes: 45b5a378 ("x86: Add multi-processor init")
Signed-off-by: NStephen Warren <swarren@nvidia.com>
Reviewed-by: NBin Meng <bmeng.cn@gmail.com>
Reviewed-by: NSimon Glass <sjg@chromium.org>
Tested-by: NBin Meng <bmeng.cn@gmail.com>

Signed-off-by: NAndreas Bießmann <andreas.devel@googlemail.com>
Cc: Gregory CLEMENT <gregory.clement@free-electrons.com>

With release of ARC HS38 v2.1 new IO coherency engine could be built-in
ARC core. This hardware module ensures coherency between DMA-ed data
from peripherals and L2 cache.

With L2 and IOC enabled there's no overhead for L2 cache manual
maintenance which results in significantly improved IO bandwidth.
Signed-off-by: NAlexey Brodkin <abrodkin@synopsys.com>

ARC core could be configured with different L1 and L2 (AKA SLC) cache
line lengths. At least these values are possible and were really used:
32, 64 or 128 bytes.

Current implementation requires cache line to be selected upon U-Boot
configuration and then it will only work on matching hardware. Indeed
this is quite efficient because cache line length gets hardcoded during
code compilation. But OTOH it makes binary less portable.

With this commit we allow U-Boot to determine real L1 cache line length
early in runtime and use this value later on. This extends portability
of U-Boot binary a lot.
Signed-off-by: NAlexey Brodkin <abrodkin@synopsys.com>