First, update the code snippet referenced in the README file. And
since there are only two boards that override flash_cmd_reset(),
might as well show them both.
Signed-off-by: NRobert P. J. Day <rpjday@crashcourse.ca>

To being able to sign created binaries, we need to know the HAB Blocks
for that image. Especially for the imximage type the HAB Blocks are
only available during creation of the image. We want to preserve the
information until we get to sign the files.
In the verbose case we still get them printed out instead of writing
to log files.

Cc: sbabic@denx.de

v2-Changes:
 - No usage of MKIMAGEOUTPUT_$(@F) macro.
 - Predefine default value /dev/null in every involved Makefile.
Signed-off-by: NSven Ebenfeld <sven.ebenfeld@gmail.com>
Reviewed-by: NGeorge McCollister <george.mccollister@gmail.com>
Tested-by: NGeorge McCollister <george.mccollister@gmail.com>

Cc: sbabic@denx.de
Signed-off-by: NSven Ebenfeld <sven.ebenfeld@gmail.com>
Reviewed-by: NGeorge McCollister <george.mccollister@gmail.com>

Przemyslaw didn't maintain the PMIC anymore.
Update the pmic maintainer from Przeymyslaw to me.
Signed-off-by: NJaehoon Chung <jh80.chung@samsung.com>
Reviewed-by: NSimon Glass <sjg@chromium.org>

Add support to handle enable-active-high DT property. This property is
used to drive the gpio controlling fixed regulator as active high when
claiming gpio line.
Signed-off-by: NVignesh R <vigneshr@ti.com>
Acked-by: NSimon Glass <sjg@chromium.org>

Fix the MMU mapping for A8K device family:
 - Separate A7K and A8K memory mappings
 - Fix memory regions by including IO mapping for all
   3 PCIe interfaces existing on each connected CP110 controller
Add A8K memory mapping documentation with all regions
configured by Marvell ATF.

Change-Id: I9c930569b1853900f5fba2d5db319b092cc7a2a6
Signed-off-by: NKonstantin Porotchkin <kostap@marvell.com>
Signed-off-by: NStefan Roese <sr@denx.de>
Cc: Stefan Roese <sr@denx.de>
Cc: Nadav Haklai <nadavh@marvell.com>
Cc: Neta Zur Hershkovits <neta@marvell.com>
Cc: Omri Itach <omrii@marvell.com>
Cc: Igal Liberman <igall@marvell.com>
Cc: Haim Boot <hayim@marvell.com>
Cc: Hanna Hawa <hannah@marvell.com>

Add pin control nodes to APN806, CP-master, CP-slave and
Armada-7040 and Armada-8040 boards DTS files
Signed-off-by: NKonstantin Porotchkin <kostap@marvell.com>
Cc: Stefan Roese <sr@denx.de>
Cc: Nadav Haklai <nadavh@marvell.com>
Cc: Neta Zur Hershkovits <neta@marvell.com>
Cc: Omri Itach <omrii@marvell.com>
Cc: Igal Liberman <igall@marvell.com>
Cc: Haim Boot <hayim@marvell.com>
Cc: Hanna Hawa <hannah@marvell.com>
Signed-off-by: NStefan Roese <sr@denx.de>

Add a DM port of Marvell pin control driver.
The A8K SoC family contains several silicone dies interconnected
in a single package. Every die is normally equipped with its own
pin controller unit.
There are 2 pin controllers in A70x0 SoC and 3 in A80x0 SoC.
Signed-off-by: NKonstantin Porotchkin <kostap@marvell.com>
Reviewed-by: NSimon Glass <sjg@chromium.org>
Cc: Simon Glass <sjg@chromium.org>
Cc: Stefan Roese <sr@denx.de>
Cc: Nadav Haklai <nadavh@marvell.com>
Cc: Neta Zur Hershkovits <neta@marvell.com>
Cc: Omri Itach <omrii@marvell.com>
Cc: Igal Liberman <igall@marvell.com>
Cc: Haim Boot <hayim@marvell.com>
Cc: Hanna Hawa <hannah@marvell.com>
Signed-off-by: NStefan Roese <sr@denx.de>

Add support for mvebu bubt command for flash image
load, check and burn on boot device.
Signed-off-by: NKonstantin Porotchkin <kostap@marvell.com>
Reviewed-by: NStefan Roese <sr@denx.de>
Cc: Stefan Roese <sr@denx.de>
Cc: Nadav Haklai <nadavh@marvell.com>
Cc: Neta Zur Hershkovits <neta@marvell.com>
Cc: Omri Itach <omrii@marvell.com>
Cc: Igal Liberman <igall@marvell.com>
Cc: Haim Boot <hayim@marvell.com>
Cc: Hanna Hawa <hannah@marvell.com>
Signed-off-by: NStefan Roese <sr@denx.de>

With the acquisition of Altera by Intel, my Altera email may be going
away soon. Update the contact to a more reliable address.
Signed-off-by: NDinh Nguyen <dinguyen@kernel.org>

Add a README with a brief guide to porting i2c drivers over to use driver
model.

Add a timeline also. All I2C drivers should be converted by the end
of June 2017.
Signed-off-by: NSimon Glass <sjg@chromium.org>
Acked-by: NHeiko Schocher <hs@denx.de>

This is not used by any boards. Drop it.
Signed-off-by: NSimon Glass <sjg@chromium.org>
Acked-by: NDavid Müller <d.mueller@elsoft.ch>
Reviewed-by: NJagan Teki <jagan@openedev.com>

This driver was converted so we should remove it from the list.
Signed-off-by: NSimon Glass <sjg@chromium.org>

To help automate the loading of custom image types we add the ability
to define custom handlers for the loadable section types. When we find
a compatible type while loading a "loadable" image from a FIT image we
run its associated handlers to perform any additional steps needed for
loading this image.
Signed-off-by: NAndrew F. Davis <afd@ti.com>
Reviewed-by: NSimon Glass <sjg@chromium.org>

Move default value definitions to to Kconfig SYS_CCSRBAR_DEFAULT.
Signed-off-by: NYork Sun <york.sun@nxp.com>

To be able to represent the skip-init platdata element with OF_CONTROL,
it needs to be read from the device tree as well and put into the platform data.

Cc: Eric Anholt <eric@anholt.net>
Signed-off-by: NFabian Vogt <fvogt@suse.com>
Reviewed-by: NSimon Glass <sjg@chromium.org>

This patch adds device tree support for the bcm283x mini-uart driver.
Signed-off-by: NFabian Vogt <fvogt@suse.com>
Reviewed-by: NSimon Glass <sjg@chromium.org>

This patch adds device tree support for the bcm2835 GPIO driver.
Signed-off-by: NFabian Vogt <fvogt@suse.com>
Reviewed-by: NSimon Glass <sjg@chromium.org>

P2010 is a single-core version of P2020. There is no P2010 target
configured. Drop related macros. P2010 SoC is still supported.
Signed-off-by: NYork Sun <york.sun@nxp.com>

P1014 is a variant of P1010. There is no P1014 target configured.
Drop related macros. P1014 SoC is still supported.
Signed-off-by: NYork Sun <york.sun@nxp.com>

P1013 is a single-core version of P1022. There is no P1022 target
configured. Drop related macros. P1022 SoC is still supported.
Signed-off-by: NYork Sun <york.sun@nxp.com>

P1012 is a single-core version of P1021. There is no P1012 target
configured. Drop related macros. P1012 SoC is still supported.
Signed-off-by: NYork Sun <york.sun@nxp.com>

This macro is no longer used.
Signed-off-by: NYork Sun <york.sun@nxp.com>

This macro is no longer used.
Signed-off-by: NYork Sun <york.sun@nxp.com>

Replace CONFIG_MPC8540 with ARCH_MPC8540 in Kconfig and clean up existing
macros.
Signed-off-by: NYork Sun <york.sun@nxp.com>

Add Jagan and Maxime as Maintainers for SUNXI
Signed-off-by: NJagan Teki <jagan@openedev.com>
Acked-by: NMaxime Ripard <maxime.ripard@free-electrons.com>

Now the flash params table as renamed to spi_flash_ids structure,
so rename the sf_params.c to spi_flash_ids.c and remove the legacy.

Cc: Bin Meng <bmeng.cn@gmail.com>
Cc: York Sun <york.sun@nxp.com>
Cc: Vignesh R <vigneshr@ti.com>
Cc: Mugunthan V N <mugunthanvnm@ti.com>
Cc: Michal Simek <michal.simek@xilinx.com>
Signed-off-by: NJagan Teki <jagan@openedev.com>
Reviewed-by: NJagan Teki <jagan@openedev.com>
Tested-by: NJagan Teki <jagan@openedev.com>
Reviewed-by: NSiva Durga Prasad Paladugu <sivadur@xilinx.com>

Enable this so that EFI applications (notably grub) can be run under U-Boot
on x86 platforms.

At present the 'hello world' EFI application is not supported for the
qemu-x86_efi_payload64 board. That board builds a payload consisting of a
64-bit header and a 32-bit U-Boot, which is incompatible with the way the
EFI loader builds its EFI application. The following error is obtained:

x86_64-linux-ld.bfd: i386 architecture of input file
   `lib/efi_loader/helloworld.o' is incompatible with i386:x86-64 output

This could be corrected with additional Makefile rules. For now, this
feature is disabled for that board.
Signed-off-by: NSimon Glass <sjg@chromium.org>
Reviewed-by: NBin Meng <bmeng.cn@gmail.com>
[agraf: drop hello kconfig bits]
Signed-off-by: NAlexander Graf <agraf@suse.de>

It is useful to have a basic sanity check for EFI loader support. Add a
'bootefi hello' command which loads HelloWord.efi and runs it under U-Boot.
Signed-off-by: NSimon Glass <sjg@chromium.org>
[agraf: Fix documentation, add unfulfilled kconfig dep]
Signed-off-by: NAlexander Graf <agraf@suse.de>

The Synopsys DWC EQoS is a configurable Ethernet MAC/DMA IP block which
supports multiple options for bus type, clocking and reset structure, and
feature list.

This patch imports the binding from the Linux kernel, including my V3
patch to extend the binding to cover the Tegra186, which is applied for
next-20160912. So far, my changes have been acked by Lars Persson, the
original author of the binding.
Signed-off-by: NStephen Warren <swarren@nvidia.com>
Reviewed-by: NSimon Glass <sjg@chromium.org>
Acked-by: NJoe Hershberger <joe.hershberger@ni.com>

Adds -i option that allows specifying a ramdisk file to be added to the
FIT image when we are using the automatic FIT mode (no ITS file).

This makes adding Depthcharge support to LAVA much more convenient, as
no additional configuration files need to be kept around in the machine
that dispatches jobs to the boards.
Signed-off-by: NTomeu Vizoso <tomeu.vizoso@collabora.com>
Cc: Simon Glass <sjg@chromium.org>
Cc: Matt Hart <matthew.hart@linaro.org>
Cc: Neil Williams <codehelp@debian.org>
Reviewed-by: NSimon Glass <sjg@chromium.org>

This file apparently hasn't seen an update in a while, so just sync
it with reality.
Signed-off-by: NAndre Przywara <andre.przywara@arm.com>

A simple introduction.
Signed-off-by: NJacob Chen <jacob2.chen@rock-chips.com>
Acked-by: NSimon Glass <sjg@chromium.org>

Signed-off-by: NJagan Teki <jagan@openedev.com>

 - Rephrase the toolchains section.  Leave only Linaro toolchains
   since it is the most tested these days.

 - Add build instruction for ARMv8 SoC boards

 - Add information about "ddrmphy" command
Signed-off-by: NMasahiro Yamada <yamada.masahiro@socionext.com>

Signed-off-by: NMasahiro Yamada <yamada.masahiro@socionext.com>

This converts coreboot to use DM framebuffer driver.
Signed-off-by: NBin Meng <bmeng.cn@gmail.com>
Reviewed-by: NSimon Glass <sjg@chromium.org>

The kernel load address for zboot should be 0x1000000.
Signed-off-by: NBin Meng <bmeng.cn@gmail.com>
Reviewed-by: NSimon Glass <sjg@chromium.org>

For some unknown reason, coreboot framebuffer driver never works on
QEMU since day 1. It seems the driver only works on real hardware.
Document this issue.
Signed-off-by: NBin Meng <bmeng.cn@gmail.com>
Reviewed-by: NSimon Glass <sjg@chromium.org>

Add device model enabled PMIC driver for Ricoh RN5T567 PMIC used
on Colibri iMX7.
Signed-off-by: NStefan Agner <stefan.agner@toradex.com>
Reviewed-by: NSimon Glass <sjg@chromium.org>