fix a stray CONFIG_MPC83XX that escaped commit
0f898604.
Signed-off-by: NKim Phillips <kim.phillips@freescale.com>
Signed-off-by: NRemy Bohmer <linux@bohmer.net>

Signed-off-by: NWolfgang Denk <wd@denx.de>

Signed-off-by: NHeiko Schocher <hs@denx.de>

This patch makes pll_write on PPC405EP boards
global and callable from C code.

pll_write can be used to dynamically modify the PLB:PCI divider
as it is required for 33/66 MHz pci adapters based on the 405EP.

board_early_init_f() is a good place to do that (check M66EN signal
and call pll_write() when it is required).
Signed-off-by: NMatthias Fuchs <matthias.fuchs@esd.eu>
Signed-off-by: NStefan Roese <sr@denx.de>

Signed-off-by: NStefan Roese <sr@denx.de>

This patch implements the is_pci_host() function in a similiar way
as it is used on 440 targets.

The former path with CONFIG_PCI_HOST == PCI_HOST_AUTO does not
build on 405EP targets because checking the PCI arbiter is different.
So putting the fixed code into a separate function makes the code
more readable.

Also using is_pci_host() on 405 brings 405 and 440 PCI code
a little bit closer.

In preparation for an upcoming 405EP based PMC module I made this
function weak so that it can be overwritten from board specific code.
Signed-off-by: NMatthias Fuchs <matthias.fuchs@esd.eu>
Signed-off-by: NStefan Roese <sr@denx.de>

This patch fixes a debug compilation error for PPC4xx platforms, all
other architectures are not affected by this change.  The 'handler'
pointer was undefined.  The fix is exercised and has effect only if
DEBUG is defined.

Signed-off-by: Alessio Centazzo acpatin@yahoo.com
Signed-off-by: NStefan Roese <sr@denx.de>

This patch fixes printf format string compilation warnings in several
debug statements. It also fixes the dump of DDR controller MQ registers
found on some 44x and 46x platforms. The current register dump code
uses incorrect DCRs to access these registers.
Signed-off-by: NFelix Radensky <felix@embedded-sol.com>
Signed-off-by: NStefan Roese <sr@denx.de>

This patch fixes 2 problems with FDT EBC mappings on Canyonlands.
First, NAND EBC mapping was missing, making Linux NAND driver
unusable on this board. Second, NOR remapping code assumed that
NOR is always on CS0, however when booting from NAND NOR is on CS3.
Signed-off-by: NFelix Radensky <felix@embedded-sol.com>
Signed-off-by: NStefan Roese <sr@denx.de>

If use the onenand boot, the env_relocate_spec() calls mtd->read(),
and the type of the argument #2 of mtd->read() was changed to loff_t.
But, the "env_addr" type is still unsigned long, thus this patch change
the type from unsigned long to loff_t.
Acked-by: NKyungmin Park <kyungmin.park@samsung.com>
Signed-off-by: NHeungJun, Kim <riverful.kim@samsung.com>
Signed-off-by: NScott Wood <scottwood@freescale.com>

The bbt descriptors contains the pointer to the bbt pattern which
are statically initialized memory struct. When relocated to RAM,
these pointers will continue point to NOR flash(or L2 SRAM, or
other boot device). If the contents of NOR flash changed or L2
SRAM disabled, it'll hang the system.
Signed-off-by: NMingkai Hu <Mingkai.hu@freescale.com>
Signed-off-by: NScott Wood <scottwood@freescale.com>

When adding large page NAND support to this file, I had a misunderstanding
about the exact semantics of NAND_CTRL_CHANGE (which isn't documented
anywhere I can find) -- it is apparently just a hint to drivers,
which aren't required to preserve the old value for subsequent
non-"change" invocations.

This change makes nand_boot.c no longer assume this.  Note that this
happened to work by chance with some NAND drivers, which don't preserve
the value, but treat 0 equivalently to NAND_CTRL_ALE.

I don't have hardware to test this, so any testing is appreciated.
Signed-off-by: NScott Wood <scottwood@freescale.com>

The S3C2410 NAND driver source file is included in the makefile instead of
the object file.
Signed-off-by: NKevin Morfitt <kevin.morfitt@fearnside-systems.co.uk>
Signed-off-by: NScott Wood <scottwood@freescale.com>

Currently, when booting from NAND using nand_spl, in the beginning the default
environment is used until later in boot process the dynamic environment is read
out. This way environment variables that must be interpreted early, like the
baudrate or "silent", cannot be modified dynamically and remain at their
default values. Fix this problem by reading out main and redundand (if used)
copies of the environment in the nand_spl code.
Signed-off-by: NGuennadi Liakhovetski <lg@denx.de>
Signed-off-by: NScott Wood <scottwood@freescale.com>

nand_util currently uses size_t which is arch dependent and not always a
unsigned long.  Now use loff_t, as does the linux mtd layer.
Signed-off-by: NJean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
Signed-off-by: NScott Wood <scottwood@freescale.com>

The "nand markbad" and "onenand markbad" commands did not check if an
argument was passed; if this was forgotten, no error was raised but
block 0 was marked as bad.

While fixing this bug, clean up the code a bit and allow to pass more
than one block address, thus allowing to mark several blocks as bad
in a single command invocation.
Signed-off-by: NWolfgang Denk <wd@denx.de>
Signed-off-by: NScott Wood <scottwood@freescale.com>

The BF537-STAMP Blackfin board had a driver for working with NAND devices
that are simply memory mapped.  Since there is nothing Blackfin specific
about this, generalize the driver a bit so that everyone can leverage it.
Signed-off-by: NMike Frysinger <vapier@gentoo.org>
Signed-off-by: NScott Wood <scottwood@freescale.com>

Remove an unused "total" variable in multiple functions.
Signed-off-by: NGuennadi Liakhovetski <lg@denx.de>
Signed-off-by: NScott Wood <scottwood@freescale.com>

Update chipselect handling in davinci_nand.c so that it can
handle 2 GByte chips the same way Linux does:  as one device,
even though it has two halves with independent chip selects.
For such chips the "nand info" command reports:

  Device 0: 2x nand0, sector size 128 KiB

Switch to use the default chipselect function unless the board
really needs its own.  The logic for the Sonata board moves out
of the driver into board-specific code.  (Which doesn't affect
current build breakage if its NAND support is enabled...)
Signed-off-by: NDavid Brownell <dbrownell@users.sourceforge.net>
Signed-off-by: NScott Wood <scottwood@freescale.com>

All DaVinci SOC's use a CLE mask of 0x10 and an ALE mask of 0x8
except the DM646x. This was decided by the design team driving the design.
This patch updates the CLE and ALE values for DM646x.
Updated patches for DM646x will be sent shortly.
This applies to u-boot-nand-flash git
Signed-off-by: NSandeep Paulraj <s-paulraj@ti.com>
Signed-off-by: NScott Wood <scottwood@freescale.com>

The ALE mask used by DaVinci SOCs is wrong. The patch changes the mask value
from '0xa' to '0x8'. This is the mask we use for all TI releases.
Signed-off-by: NSandeep Paulraj <s-paulraj@ti.com>
Signed-off-by: NScott Wood <scottwood@freescale.com>

Remove CONFIG_SYS_DAVINCI_BROKEN_ECC option.  It's not just nasty;
it's also unused by any current boards, and doesn't even match the
main U-Boot distributions from TI (which use soft ECC, or 4-bit ECC
on newer chips that support it).

DaVinci GIT kernels since 2.6.24, and mainline Linux since 2.6.30,
match non-BROKEN code paths for 1-bit HW ECC.  The BROKEN code paths
do seem to partially match what MontaVista/TI kernels (4.0/2.6.10,
and 5.0/2.6.18) do ... but only for small pages.  Large page support
is really broken (and it's unclear just what software it was trying
to match!), and the ECC layout was making three more bytes available
for use by filesystem (or whatever) code.

Since this option itself seems broken, remove it.  Add a comment
about the MV/TI compat issue, and the most straightforward way to
address it (should someone really need to solve it).
Signed-off-by: NDavid Brownell <dbrownell@users.sourceforge.net>
Signed-off-by: NScott Wood <scottwood@freescale.com>

Minor cleanup for DaVinci NAND code:

 - Use I/O addresses from nand_chip; CONFIG_SYS_NAND_BASE won't
   be defined when there are multiple chipselect lines in use
   (as with common 2 GByte chips).

 - Cleanup handling of EMIF control registers
    * Only need one pointer pointing to them
    * Remove incorrect and unused struct supersetting them

 - Use the standard waitfunc; we don't need a custom version

 - Partial legacy cleanup:
    * Don't initialize every board like it's a DM6446 EVM
    * #ifdef a bit more code for BROKEN_ECC

Sanity checked with small page NAND on dm355 and dm6446 EVMs;
and large page on dm355 EVM (packaged as two devices, not one).
Signed-off-by: NDavid Brownell <dbrownell@users.sourceforge.net>
Signed-off-by: NScott Wood <scottwood@freescale.com>

Signed-off-by: NWolfgang Denk <wd@denx.de>

Conflicts:
	drivers/spi/Makefile
Signed-off-by: NWolfgang Denk <wd@denx.de>

This patch fixes a build problem noticed on Apollon by using
mtd_dev_by_eb() instead of "/" as done in the Linux UBI version.
So this brings the U-Boot UBI version more in sync with the Linux
version again.
Signed-off-by: NStefan Roese <sr@denx.de>

new chips supported:-
MX25L1605D, MX25L3205D, MX25L6405D, MX25L12855E
out of which MX25L6405D and MX25L12855E tested on Kirkwood platforms

Modified the Macronix flash support to use 2 bytes of device id instead of 1
This was required to support MX25L12855E
Signed-off-by: NPiyush Shah <spiyush@marvell.com>
Signed-off-by: NPrafulla Wadaskar <prafulla@marvell.com>
Signed-off-by: NMike Frysinger <vapier@gentoo.org>

Signed-off-by: NMike Frysinger <vapier@gentoo.org>

Looks like when I was encoding the sector sizes, I forgot to divide by 8
(due to the stupid marketing driven process that declares all sizes in
useless megabits and not megabytes).
Signed-off-by: NMike Frysinger <vapier@gentoo.org>

Signed-off-by: NJean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>

Signed-off-by: NMagnus Lilja <lilja.magnus@gmail.com>

This patch abstracts Kirkwood arch specific changes to support ehci-kirkwood driver
Signed-off-by: NPrafulla Wadaskar <prafulla@marvell.com>