- 04 7月, 2018 3 次提交
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由 Andre Przywara 提交于
The Allwinner A64 SoCs suffers from an arch timer implementation erratum, where sometimes the lower 11 bits of the counter value erroneously become all 0's or all 1's [1]. This leads to sudden jumps, both forwards and backwards, with the latter one often showing weird behaviour. Port the workaround proposed for Linux to U-Boot and activate it for all A64 boards. This fixes crashes when accessing MMC devices (SD cards), caused by a recent change to actually use the counter value for timeout checks. Fixes: 5ff8e548 ("sunxi: improve throughput in the sunxi_mmc driver") [1] http://lists.infradead.org/pipermail/linux-arm-kernel/2018-May/576886.htmlSigned-off-by: NAndre Przywara <andre.przywara@arm.com> Reviewed-by: NPhilipp Tomsich <philipp.tomsich@theobroma-systems.com> Tested-by: NJagan Teki <jagan@amarulasolutions.com> Tested-by: NAndreas Färber <afaerber@suse.de> Tested-by: NGuillaume Gardet <guillaume.gardet@free.fr>
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由 Andre Przywara 提交于
At the moment we have the workaround for the Freescale arch timer erratum A-008585 merged into the generic timer_read_counter() routine. Split those two up, so that we can add other errata workaround more easily. Also add an explaining comment on the way. Signed-off-by: NAndre Przywara <andre.przywara@arm.com> Tested-by: NJagan Teki <jagan@amarulasolutions.com> Tested-by: NAndreas Färber <afaerber@suse.de> Tested-by: NGuillaume Gardet <guillaume.gardet@free.fr>
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- 03 7月, 2018 12 次提交
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由 Tom Rini 提交于
Signed-off-by: NTom Rini <trini@konsulko.com>
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由 Tom Rini 提交于
The various Aries Embedded boards have been orphaned for a year and no one has come forward to take care of them. Remove. Signed-off-by: NTom Rini <trini@konsulko.com>
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由 Alexander Graf 提交于
The ax25-ae350 target currently uses CONFIG_BOOTP_SERVERIP which means we ignore the DHCP provided TFTP ip address. This breaks every case where we do now provide a serverip environment variable. Instead, let's use the new CONFIG_BOOT_PREFER_SERVERIP option to fall back to the DHCP provided TFTP IP if no serverip environment variable is set. Signed-off-by: NAlexander Graf <agraf@suse.de> Acked-by: NJoe Hershberger <joe.hershberger@ni.com> Acked-by: NRick Chen <rick@andestech.com>
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由 Alexander Graf 提交于
Currently we can choose between 2 different types of behavior for the serverip variable: 1) Always overwrite it with the DHCP server IP address (default) 2) Ignore what the DHCP server says (CONFIG_BOOTP_SERVERIP) This patch adds a 3rd option: 3) Use serverip from DHCP if no serverip is given (CONFIG_BOOTP_PREFER_SERVERIP) With this new option, we can have the default case that a boot file gets loaded from the DHCP provided TFTP server work while allowing users to specify their own serverip variable to explicitly use a different tftp server. Signed-off-by: NAlexander Graf <agraf@suse.de> Acked-by: NJoe Hershberger <joe.hershberger@ni.com>
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由 Alexander Graf 提交于
We can call commands like dhcp and bootp without arguments or with explicit command line arguments that really should tell the code where to look for files instead. Unfortunately, the current code simply overwrites command line arguments in the dhcp case with dhcp values. This patch allows the code to preserve the command line values if they were set on the command line. That way the semantics are slightly more intuitive. The reason this patch does that by introducing a new variable is that we can not rely on net_boot_file_name[0] being unset, as today it's completely legal to call "dhcp" and afterwards run "tftp" and expect the latter to repeat the same query as before. I would prefer not to break that behavior in case anyone relies on it. Signed-off-by: NAlexander Graf <agraf@suse.de> Acked-by: NJoe Hershberger <joe.hershberger@ni.com>
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由 Lothar Felten 提交于
Add a new command 'wol': Wait for an incoming Wake-on-LAN packet or time out if no WoL packed is received. If the WoL packet contains a password, it is saved in the environment variable 'wolpassword' using the etherwake format (dot or colon separated decimals). Intended use case: a networked device should boot an alternate image. It's attached to a network on a client site, modifying the DHCP server configuration or setup of a tftp server is not allowed. After power on the device waits a few seconds for a WoL packet. If a packet is received, the device boots the alternate image. Otherwise it boots the default image. This method is a simple way to interact with a system via network even if only the MAC address is known. Tools to send WoL packets are available on all common platforms. Some Ethernet drivers seem to pad the incoming packet. The additional padding bytes might be recognized as Wake-on-LAN password bytes. By default enabled in pengwyn_defconfig. Signed-off-by: NLothar Felten <lothar.felten@gmail.com> Acked-by: NJoe Hershberger <joe.hershberger@ni.com>
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由 Rabeeh Khoury 提交于
Make the initialization sequence consistent with the Linux kernel driver. Reviewed-by: NStefan Roese <sr@denx.de> Acked-by: NJoe Hershberger <joe.hershberger@ni.com> Signed-off-by: NRabeeh Khoury <rabeeh@solid-run.com> Signed-off-by: NBaruch Siach <baruch@tkos.co.il>
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由 Rabeeh Khoury 提交于
This fixes sporadic timeout on initial packet Tx (usually ARP), with an error message like: timeout: packet not sent Reviewed-by: NStefan Roese <sr@denx.de> Tested-by: NChris Packham <judge.packham@gmail.com> Acked-by: NJoe Hershberger <joe.hershberger@ni.com> Signed-off-by: NRabeeh Khoury <rabeeh@solid-run.com> Signed-off-by: NBaruch Siach <baruch@tkos.co.il>
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由 Alex Kiernan 提交于
When building without FASTBOOT_FLASH we don't include the intermediate update callback to keep the client alive, so ensure we don't try setting it here. Signed-off-by: NAlex Kiernan <alex.kiernan@gmail.com> Acked-by: NJoe Hershberger <joe.hershberger@ni.com>
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由 Michal Simek 提交于
phyread can timeout and val will contain random value. Initialize it to zero not to report random value in case of error. Signed-off-by: NMichal Simek <michal.simek@xilinx.com> Acked-by: NJoe Hershberger <joe.hershberger@ni.com>
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- 02 7月, 2018 11 次提交
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由 Tom Rini 提交于
As pointed out by Wolfgang Denk, the problem with this fix is that while interactive users will see that we have found one part of the environment failed and are using the other, progmatic use will not see this and can lead to problems. Signed-off-by: NTom Rini <trini@konsulko.com>
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由 Bin Meng 提交于
This updates the doc to mention chain-loading an x86 kernel via 'bootefi' command, along with several typos fix. Signed-off-by: NBin Meng <bmeng.cn@gmail.com> Reviewed-by: NSimon Glass <sjg@chromium.org> Reviewed-by: NAlexander Graf <agraf@suse.de>
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由 Bin Meng 提交于
CONFIG_EFI_LOADER is fully supported on x86 now. Signed-off-by: NBin Meng <bmeng.cn@gmail.com> Reviewed-by: NSimon Glass <sjg@chromium.org> Reviewed-by: NAlexander Graf <agraf@suse.de>
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由 Bin Meng 提交于
Output ACPI configuration table if it exists. Signed-off-by: NBin Meng <bmeng.cn@gmail.com> Reviewed-by: NHeinrich Schuchardt <xypron.glpk@gmx.de>
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由 Bin Meng 提交于
ACPI tables can be passed via EFI configuration table to an EFI application. This is only supported on x86 so far. Signed-off-by: NBin Meng <bmeng.cn@gmail.com> Reviewed-by: NSimon Glass <sjg@chromium.org>
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由 Bin Meng 提交于
At present the number of configuration tables is set to 2. By looking at which tables the Linux EFI stub or iPXE can process, it looks 16 is a reasonable number. Signed-off-by: NBin Meng <bmeng.cn@gmail.com> Reviewed-by: NHeinrich Schuchardt <xypron.glpk@gmx.de>
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由 Bin Meng 提交于
On x86 traditional E820 table is used to pass the memory information to kernel. With EFI loader we can build the EFI memory map from it. Signed-off-by: NBin Meng <bmeng.cn@gmail.com> Reviewed-by: NSimon Glass <sjg@chromium.org>
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由 Ivan Gorinov 提交于
Built without a ROM image with FSP (u-boot.rom), the U-Boot loader applies the microcode update data block encoded in Device Tree to the bootstrap processor but not passed to the other CPUs when multiprocessing is enabled. If the bootstrap processor successfully performs a microcode update from Device Tree, use the same data block for the other processors. Signed-off-by: NIvan Gorinov <ivan.gorinov@intel.com> Reviewed-by: NBin Meng <bmeng.cn@gmail.com> [bmeng: fixed build errors on edison and qemu-x86] Signed-off-by: NBin Meng <bmeng.cn@gmail.com>
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由 Bin Meng 提交于
This adds the scsi command to coreboot and qemu, to be in consistent with other x86 targets. Signed-off-by: NBin Meng <bmeng.cn@gmail.com> Reviewed-by: NSimon Glass <sjg@chromium.org>
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由 Bin Meng 提交于
With the introduction of early timer support in the TSC driver, the capability of getting clock rate from device tree was lost unfortunately. Now we bring such functionality back, but with a limitation that when TSC is used as early timer, specifying clock rate from device tree does not work. This fixes random boot failures seen on QEMU targets: printing "TSC frequency is ZERO" and reset forever. Signed-off-by: NBin Meng <bmeng.cn@gmail.com> Reviewed-by: NSimon Glass <sjg@chromium.org>
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- 30 6月, 2018 2 次提交
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由 Fabio Estevam 提交于
On a 4.18-rc1 kernel the following warning is seen on i.MX51 and i.MX53: CPU0: Spectre v2: firmware did not set auxiliary control register IBE bit, system vulnerable Select the ARM_CORTEX_A8_CVE_2017_5715 workaround for i.MX51/i.MX53 to fix the problem. With this patch applied the kernel reports: CPU0: Spectre v2: using BPIALL workaround Signed-off-by: NFabio Estevam <fabio.estevam@nxp.com>
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- 29 6月, 2018 9 次提交
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由 Heinrich Schuchardt 提交于
%s/reminder/remainder/ Signed-off-by: NHeinrich Schuchardt <xypron.glpk@gmx.de>
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由 Nishanth Menon 提交于
Enable CVE-2017-5715 option to set the IBE bit. This enables kernel workarounds necessary for the said CVE. With this enabled, Linux reports: CPU0: Spectre v2: using BPIALL workaround This workaround may need to be re-applied in OS environment around low power transition resume states where context of ACR would be lost (off-mode etc). Signed-off-by: NNishanth Menon <nm@ti.com>
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由 Nishanth Menon 提交于
ARM: mach-omap2: omap5/dra7: Enable ACTLR[0] (Enable invalidates of BTB) to facilitate CVE_2017-5715 WA in OS Enable CVE_2017_5715 and since we have our own v7_arch_cp15_set_acr function to setup the bits, we are able to override the settings. Without this enabled, Linux kernel reports: CPU0: Spectre v2: firmware did not set auxiliary control register IBE bit, system vulnerable With this enabled, Linux kernel reports: CPU0: Spectre v2: using ICIALLU workaround NOTE: This by itself does not enable the workaround for CPU1 (on OMAP5 and DRA72/AM572 SoCs) and may require additional kernel patches. Signed-off-by: NNishanth Menon <nm@ti.com>
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由 Nishanth Menon 提交于
As recommended by Arm in [1], ACTLR[0] (Enable invalidates of BTB) needs to be set[2] for BTB to be invalidated on ICIALLU. This needs to be done unconditionally for Cortex-A15 processors. Provide a config option for platforms to enable this option based on impact analysis for products. NOTE: This patch in itself is NOT the final solution, this requires: a) Implementation of v7_arch_cp15_set_acr on SoCs which may not provide direct access to ACR register. b) Operating Systems such as Linux to provide adequate workaround in the right locations. c) This workaround applies to only the boot processor. It is important to apply workaround as necessary (context-save-restore) around low power context loss OR additional processors as necessary in either firmware support OR elsewhere in OS. [1] https://developer.arm.com/support/security-update [2] http://infocenter.arm.com/help/topic/com.arm.doc.ddi0438c/BABGHIBG.html Cc: Marc Zyngier <marc.zyngier@arm.com> Cc: Russell King <linux@arm.linux.org.uk> Cc: Tony Lindgren <tony@atomide.com> Cc: Robin Murphy <robin.murphy@arm.com> Cc: Florian Fainelli <f.fainelli@gmail.com> Cc: Catalin Marinas <catalin.marinas@arm.com> Cc: Will Deacon <will.deacon@arm.com> Cc: Christoffer Dall <christoffer.dall@linaro.org> Cc: Andre Przywara <Andre.Przywara@arm.com> Cc: Ard Biesheuvel <ard.biesheuvel@linaro.org> Cc: Tom Rini <trini@konsulko.com> Cc: Michael Nazzareno Trimarchi <michael@amarulasolutions.com> Signed-off-by: NNishanth Menon <nm@ti.com> Tested-by: NFabio Estevam <fabio.estevam@nxp.com>
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由 Nishanth Menon 提交于
As recommended by Arm in [1], IBE[2] has to be enabled unconditionally for BPIALL to be functional on Cortex-A8 processors. Provide a config option for platforms to enable this option based on impact analysis for products. NOTE: This patch in itself is NOT the final solution, this requires: a) Implementation of v7_arch_cp15_set_acr on SoCs which may not provide direct access to ACR register. b) Operating Systems such as Linux to provide adequate workaround in the right locations. c) This workaround applies to only the boot processor. It is important to apply workaround as necessary (context-save-restore) around low power context loss OR additional processors as necessary in either firmware support OR elsewhere in OS. [1] https://developer.arm.com/support/security-update [2] http://infocenter.arm.com/help/topic/com.arm.doc.ddi0344k/Bgbffjhh.html Cc: Marc Zyngier <marc.zyngier@arm.com> Cc: Russell King <linux@arm.linux.org.uk> Cc: Tony Lindgren <tony@atomide.com> Cc: Robin Murphy <robin.murphy@arm.com> Cc: Florian Fainelli <f.fainelli@gmail.com> Cc: Catalin Marinas <catalin.marinas@arm.com> Cc: Will Deacon <will.deacon@arm.com> Cc: Christoffer Dall <christoffer.dall@linaro.org> Cc: Andre Przywara <Andre.Przywara@arm.com> Cc: Ard Biesheuvel <ard.biesheuvel@linaro.org> Cc: Tom Rini <trini@konsulko.com> Cc: Michael Nazzareno Trimarchi <michael@amarulasolutions.com> Signed-off-by: NNishanth Menon <nm@ti.com> Tested-by: NFabio Estevam <fabio.estevam@nxp.com>
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由 Jagan Teki 提交于
Masking clock gate, reset register bits based on the probed controller is proper only due to the assumption that masking should start with 0 even thought the controller has separate PHY or shared between OTG. unfortunately these are fixed due to lack of separate clock, reset drivers. Say for example EHCI1 - EHCI3 in the datasheet (EHCI0 is for the OTG) so we need to start reg_mask 0 - 2. This patch calculated the mask, based on the register base so that we can get the proper bits to set with respect to probed controller. We even do this masking by using PHY index specifier from dt, but dev_read_addr_size is failing for 64-bit boards. Signed-off-by: NJagan Teki <jagan@amarulasolutions.com>
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由 Jagan Teki 提交于
This patch update the USB PHY index for Allwinner H3. Same change[1] initially sent, by 'Chen-Yu Tai' but missed to apply due to recursive version changes on the same series. [1] https://lists.denx.de/pipermail/u-boot/2018-January/318817.htmlSigned-off-by: NJagan Teki <jagan@amarulasolutions.com>
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由 Zeng Tao 提交于
For ohci, the maximam supported endpoint number is 32(in and out), and now we have used (usb_pipeendpoint(pipe) << 1) to index the specified endpoint descritor, usb_pipeendpoint(pipe) can reach 0xf, so we need change the NUM_EDs from 8 to 32. Signed-off-by: NZeng Tao <prime.zeng@hisilicon.com>
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由 Vasily Khoruzhick 提交于
ohci-hcd casts priv_data pointer to (ohci_t *), thus it must be the first member in private data struct. Fixes 831cc98b ("usb: sunxi: Simplify ccm reg base code") Signed-off-by: NVasily Khoruzhick <anarsoul@gmail.com>
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- 28 6月, 2018 3 次提交
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由 Marek Vasut 提交于
The N25Q256(A) datasheet clearly states that this device does have a Flag Status Register and does update FSR PEC bit 7 during Program and Erase cycles to indicate the cycle is in progress. Enable the FSR PEC bit polling on this device to prevent data corruption. Signed-off-by: NMarek Vasut <marex@denx.de> Cc: Jagan Teki <jagan@openedev.com> Cc: Tom Rini <trini@konsulko.com>
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由 Hannes Schmelzer 提交于
The claim/release bus function must not reset the whole SPI core because settings regarding wordlen, clock-frequency and so on made by set_wordlen, set_mode, set_speed get lost with this action. Resulting in a non-functional SPI. Without DM the failure didn't came up since after the spi_reset within claim bus all the setup (wordlen, mode, ...) was called, in DM they are called by the spi uclass. We change now the things as following for having a working SPI instance in DM: - move the spi_reset(...) to the probe call in DM for having a known hardware state after probe. Without DM we don't have a probe call, so we issue the reset as before during the claim_bus call. - in release bus we just reset the modulctrl to the reset-value (spi- slave) Signed-off-by: NHannes Schmelzer <oe5hpm@oevsv.at> Reviewed-by: NJagan Teki <jagan@openedev.com>
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