In the newer versions of designware i2c IP there is the possibility
of configuring it with IC_EMPTYFIFO_HOLD_MASTER_EN=1, which basically
requires the s/w to generate the stop bit condition directly, as
the h/w will not automatically generate it when TX_FIFO is empty.

To avoid generation of an extra 0x0 byte sent as data, the
IC_STOP command must be sent along with the last IC_CMD.

This patch always writes bit[9] of ic_data_cmd even in the
older versions, assuming that it is a noop there.
Signed-off-by: NArmando Visconti <armando.visconti@st.com>

This patch adds the capability to switch between 10
different I2C busses (from 0 to 9).
Signed-off-by: NArmando Visconti <armando.visconti@st.com>

This patch modifies the S3C i2c driver to support both Exynos4 and Exynos5
Signed-off-by: NPiotr Wilczek <p.wilczek@samsung.com>
Signed-off-by: NKyungmin Park <kyungmin.park@samsung.com>
CC: Minkyu Kang <mk7.kang@samsung.com>

This patch add pinmux for I2C for Exynos4
Signed-off-by: NPiotr Wilczek <p.wilczek@samsung.com>
Signed-off-by: NKyungmin Park <kyungmin.park@samsung.com>
CC: Minkyu Kang <mk7.kang@samsung.com>

This patch add the spacing for i2c for Exynos4
Signed-off-by: NPiotr Wilczek <p.wilczek@samsung.com>
Signed-off-by: NKyungmin Park <kyungmin.park@samsung.com>
CC: Minkyu Kang <mk7.kang@samsung.com>

This patch adds i2c clock for Exynos4
Signed-off-by: NPiotr Wilczek <p.wilczek@samsung.com>
Signed-off-by: NKyungmin Park <kyungmin.park@samsung.com>
CC: Minkyu Kang <mk7.kang@samsung.com>

OMAP5 has 8b i2c data register field, like OMAP2, 3 and 4. Handle in the same
way. This fixes the following error on OMAP5:

  OMAP5430 EVM # mmc rescan
  timed out in wait_for_bb: I2C_STAT=1410
  twl6035: could not turn on LDO9.
Signed-off-by: NVincent Stehlé <v-stehle@ti.com>

This algorithm computes the values of TIMING{0,1,2} registers for the
MX28 I2C block. This algorithm was derived by using a scope, but the
result seems correct.

The resulting values programmed into the registers do not correlate
with the contents in datasheet. When using the values from the datasheet,
the I2C clock were completely wrong.
Signed-off-by: NMarek Vasut <marex@denx.de>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Fabio Estevam <fabio.estevam@freescale.com>
Cc: Wolfgang Denk <wd@denx.de>

The I2C block reset configures the I2C bus speed to strange value.
Read the I2C speed from the block before reseting the block and
restore it afterwards, so the I2C operates correctly. This issue
can be replicated by doing unsuccessful I2C transfer, after such
transfer finishes, the I2C block clock speed is misconfigured.
Signed-off-by: NMarek Vasut <marex@denx.de>
Cc: Heiko Schocher <hs@denx.de>
Cc: Fabio Estevam <fabio.estevam@freescale.com>

According to FSL, the value in the TIMING2 register shall be 0x00300030
instead of what's written in the datasheet. This new value correlates
with older STMP36xx datasheet. Issues were detected in Linux when this
register was misconfigured, so write this correct value.
Signed-off-by: NMarek Vasut <marex@denx.de>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Fabio Estevam <fabio.estevam@freescale.com>

Use i2c_set_bus_speed() in i2c_init() within the mxs i2c driver
to avoid duplication of code.
Signed-off-by: NMarek Vasut <marex@denx.de>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Fabio Estevam <fabio.estevam@freescale.com>

This patch implements the setup and retrieval functions for the I2C
bus speed on the MXS I2C IP.
Signed-off-by: NMarek Vasut <marex@denx.de>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Fabio Estevam <fabio.estevam@freescale.com>

This patch pulls out the I2C speed setup from the i2c_init() call
and implements the bus configuration lookup table with register
values that needs to be programmed into the I2C IP to run at
particular speed.

This patch is a first step towards implementing run-time I2C bus
speed configuration for the MXS I2C IP.
Signed-off-by: NMarek Vasut <marex@denx.de>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Fabio Estevam <fabio.estevam@freescale.com>

Add kerneldoc style documentation into cmd_i2c.c to properly describe
all overridable functions and most of the command interface.
Signed-off-by: NMarek Vasut <marex@denx.de>
Cc: Heiko Schocher <hs@denx.de>

Some functions in the MXC i2c driver were not static, fix this by
making them so.
Signed-off-by: NMarek Vasut <marex@denx.de>
Cc: Heiko Schocher <hs@denx.de>
Cc: Stefano Babic <sbabic@denx.de>

Use __weak from linux/compiler.h instead of __attribute__((weak, alias))
to define overridable function. This patch is intended as a cleanup patch
to bring some consistency into the code.
Signed-off-by: NMarek Vasut <marex@denx.de>
Cc: Heiko Schocher <hs@denx.de>

Signed-off-by: NAndreas Bießmann <biessmann@corscience.de>

Signed-off-by: NLars Rasmusson <Lars.Rasmusson@sics.se>

Fix several warnings when enabling UBIFS on MIPS:

In file included from ubifs.h:2137:0,
                 from ubifs.c:26:
misc.h: In function 'ubifs_zn_dirty':
misc.h:38:2: warning: passing argument 2 of 'test_bit' discards 'const' qualifier from pointer target type [enabled by default]
../include/asm/bitops.h:569:23: note: expected 'volatile void *' but argument is of type 'const long unsigned int *'
Signed-off-by: NDaniel Schwierzeck <daniel.schwierzeck@gmail.com>

If bal is 8 bytes aligned, the _gp will not be 8 bytes aligned.
then the following ld insntrustion generates a Adel exception.
So here make _gp be always aligned in 8 bytes.
Signed-off-by: NZhi-zhou Zhang <zhizhou.zh@gmail.com>
Signed-off-by: NDaniel Schwierzeck <daniel.schwierzeck@gmail.com>

The filename buffer is allocated dynamically. It must be cache aligned.
Moreover, it is necessary to erase its content before we use it for
file name operations.

This prevents from corruption of written file names.
Signed-off-by: NLukasz Majewski <l.majewski@samsung.com>
Signed-off-by: NKyungmin Park <kyungmin.park@samsung.com>

Several fixes to suppress compiler's (eldk-5.[12].x  gcc 4.6)
warning  [-Wunused-but-set-variable]
Signed-off-by: NLukasz Majewski <l.majewski@samsung.com>
Signed-off-by: NKyungmin Park <kyungmin.park@samsung.com>

The device block descriptor (block_dev_desc_t) )shall be stored at
ext4 early code (at ext4fs_set_blk_dev in this case) to be available
for latter use (like put_ext4()).
Signed-off-by: NLukasz Majewski <l.majewski@samsung.com>
Signed-off-by: NKyungmin Park <kyungmin.park@samsung.com>

The ext4write code has been using direct calls to 64-32 division
(/ and %).

Officially supported u-boot toolchains (eldk-5.[12].x) generate calls
to __aeabi_uldivmod(), which is niether defined in the toolchain libs
nor u-boot source tree.

Due to that, when the ext4write command has been executed, "undefined
instruction" execption was generated (since the __aeabi_uldivmod()
is not provided).

To fix this error, lldiv() for division and do_div() for modulo have
been used.

Those two functions are recommended for performing 64-32 bit number
division in u-boot.
Signed-off-by: NLukasz Majewski <l.majewski@samsung.com>
Signed-off-by: NKyungmin Park <kyungmin.park@samsung.com>

Change e-mail address of Luka Perkov.
Signed-off-by: NLuka Perkov <luka@openwrt.org>
CC: Luka Perkov <uboot@lukaperkov.net>

If the pl011 is connected to another device which has hardware
flow-control on, characters are never received by the pl011.
Asserting RTS when flow-control is off will have no effect.

This is in line with how Linux behaves.
Signed-off-by: NJoshua Housh <joshua.housh@calxeda.com>
Tested-by: NMarek Vasut <marex@denx.de>

Since there's no obvious mention, add a brief reference to the
custodians page at www.denx.de
Signed-off-by: NRobert P. J. Day <rpjday@crashcourse.ca>

The config is current broken. It compiles but does not boot because IDE is
enabled. Remove all IDE options, and enable SCSI instead.

Also add a working boot command and Linux bootargs, and enable command
line editing to make it easier to work with.
Signed-off-by: NSimon Glass <sjg@chromium.org>

This allows u-boot to figure out the partitions of a chrome-os install.
Signed-off-by: NGabe Black <gabeblack@chromium.org>
Signed-off-by: NSimon Glass <sjg@chromium.org>

Enable the display on coreboot, using CFB.
Signed-off-by: NSimon Glass <sjg@chromium.org>

When running from coreboot we don't want this code, so make it
optional.
Signed-off-by: NSimon Glass <sjg@chromium.org>

This function is not intended to be exported from the video drivers, so
remove the prototype. This fixes an error:

cfb_console.c:1793:12: error: static declaration of 'video_init' follows non-static declaration
Signed-off-by: NSimon Glass <sjg@chromium.org>

This command will start erasing at memory address zero
if there is not a valid framebuffer address that was found
during video_init().

This is a common case with Chrome OS devices in normal mode
when we do not execute the video option rom in coreboot.
Signed-off-by: NDuncan Laurie <dlaurie@chromium.org>
Signed-off-by: NSimon Glass <sjg@chromium.org>

The function setup_pcat_compatibility() is weak and implemented as empty
function in board.c hence we don't have to override that with another
empty function.

monitor_flash_len is unused, drop it.
Signed-off-by: NStefan Reinauer <reinauer@chromium.org>
Signed-off-by: NSimon Glass <sjg@chromium.org>

... because that information is already "encoded" in the directory name.
Signed-off-by: NStefan Reinauer <reinauer@chromium.org>
Signed-off-by: NSimon Glass <sjg@chromium.org>

Some systems (like Google Link device) provide the ability to keep a
history of the target CPU port80 accesses, which is extremely handy
for debugging. The problem is that the EC handling port 80 access is
orders of magnitude slower than the AP. This causes random loss of
trace data.

This change allows to throttle port 80 accesses such that in case the
AP is trying to post faster than the EC can handle, a delay is
introduced to make sure that the post rate is throttled. Experiments
have shown that on Link the delay should be at least 350,000 of tsc
clocks.

Throttling is not being enabled by default: to enable it one would
have to set MIN_PORT80_KCLOCKS_DELAY to something like 400 and rebuild
the u-boot image. With upcoming EC code optimizations this number
could be decreased (new new value should be established
experimentally).
Signed-off-by: NVadim Bendebury <vbendeb@chromium.org>
Signed-off-by: NSimon Glass <sjg@chromium.org>

Some u-boot modules rely on availability of get_ticks() and
get_tbclk() functions, reporting a free running clock and its
frequency respectively. Traditionally these functions return number
and frequency of timer interrupts.

Intel's core architecture processors however are known to run the
rdtsc instruction at a constant rate of the so called 'Max Non Turbo
ratio' times the external clock frequency which is 100MHz. This is
just as good for the timer tick functions in question.
Signed-off-by: NVadim Bendebury <vbendeb@chromium.org>
Signed-off-by: NSimon Glass <sjg@chromium.org>

This will write magic value to APMC command port which
will trigger an SMI and cause coreboot to lock down
the ME, chipset, and CPU.
Signed-off-by: NDuncan Laurie <dlaurie@chromium.org>
Signed-off-by: NSimon Glass <sjg@chromium.org>

Coreboot was always using MTRR 7 for the write-protect
cache entry that covers the ROM and U-boot was removing it.
However with 4GB configs we need more MTRRs for the BIOS
and so the WP MTRR needs to move.  Instead coreboot will
always use the last available MTRR that is normally set
aside for OS use and U-boot can clear it before the OS.
Signed-off-by: NDuncan Laurie <dlaurie@chromium.org>
Signed-off-by: NSimon Glass <sjg@chromium.org>