- 15 11月, 2016 17 次提交
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由 Michal Simek 提交于
Do not setup use_alt bit which copy alternative boot mode to boot mode. The reason is that this bit is cleared after POR but not after any software reset which will cause that after SW reset bootrom will look for different boot image. This patch setups alternative boot mode selection (purely SW handling) and extends code to read this alternative boot mode first and use it if it is setup. Signed-off-by: NMichal Simek <michal.simek@xilinx.com>
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Add support for SD1 with level shifters bootmode. Signed-off-by: NSiva Durga Prasad Paladugu <sivadur@xilinx.com> Signed-off-by: NMichal Simek <michal.simek@xilinx.com>
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由 Michal Simek 提交于
Signed-off-by: NMichal Simek <michal.simek@xilinx.com>
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由 Soren Brinkmann 提交于
The new FW interface returns the IDCODE and version register, leaving extracting bitfields to the caller. Cc: Michal Simek <michal.simek@xilinx.com> Cc: Siva Durga Prasad Paladugu <sivadur@xilinx.com> Signed-off-by: NSoren Brinkmann <soren.brinkmann@xilinx.com> Signed-off-by: NMichal Simek <michal.simek@xilinx.com>
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由 Michal Simek 提交于
Zynq 7000S (Single A9 core) devices is using different ID code. This patch adds this new codes and assign them. Signed-off-by: NMichal Simek <michal.simek@xilinx.com>
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Correct the SGMII enable bit position to 27 instead of 31. Signed-off-by: NSiva Durga Prasad Paladugu <sivadur@xilinx.com> Signed-off-by: NMichal Simek <michal.simek@xilinx.com> Acked-by: NJoe Hershberger <joe.hershberger@ni.com>
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Modify the nwcfg bit definitions to have 32-bit by removing the extra nibble. Signed-off-by: NSiva Durga Prasad Paladugu <sivadur@xilinx.com> Signed-off-by: NMichal Simek <michal.simek@xilinx.com> Acked-by: NJoe Hershberger <joe.hershberger@ni.com>
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Clear ecc ON bit while sending read command as all types of read command(like reading spare) doesnt need ECC to be enabled. It has been anyway taken care in other places whereever required using arasan_nand_enable_ecc(). Signed-off-by: NSiva Durga Prasad Paladugu <sivadur@xilinx.com> Signed-off-by: NMichal Simek <michal.simek@xilinx.com>
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由 Michal Simek 提交于
This patch adds support to check the buswidth on nand flash at runtime based on nand MIO configurations done by FSBL. User needs to correctly configure the MIO's based on the buswidth supported by the nand flash which is present on the board. Added nand8 and nand16 @periph names on slcr driver. Signed-off-by: NJagannadha Sutradharudu Teki <jaganna@xilinx.com> Signed-off-by: NMichal Simek <michal.simek@xilinx.com>
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Enable zynq Nand flash controller driver for a zynq ZC770 XM011(dc2) board. Signed-off-by: NSiva Durga Prasad Paladugu <sivadur@xilinx.com> Signed-off-by: NMichal Simek <michal.simek@xilinx.com>
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Add nand flash controller driver support for zynq SoC. Signed-off-by: NSiva Durga Prasad Paladugu <sivadur@xilinx.com> Signed-off-by: NMichal Simek <michal.simek@xilinx.com>
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由 Mike Looijmans 提交于
The topic-miami SoMs contain a Zynq xc7z015 or xc7z030 SoC, 1GB DDR3L RAM, 32MB QSPI NOR flash and 256MB NAND flash. The topic-miamiplus SoMs contain a Zynq xc7z035, xc7z045 or xc7z100 SoC, 2x 1GB DDR3L RAM, 64MB dual-parallel QSPI flash, clock sources and a fan controller. The "Florida" carrier boards add SD, USB, ethernet and other interfaces. Signed-off-by: NMike Looijmans <mike.looijmans@topic.nl> Signed-off-by: NMichal Simek <michal.simek@xilinx.com>
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由 Mike Looijmans 提交于
Add a string description for SYS_VENDOR to allow configuring boards from other vendors than just "xilinx". Signed-off-by: NMike Looijmans <mike.looijmans@topic.nl> Signed-off-by: NMichal Simek <michal.simek@xilinx.com>
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由 Michal Simek 提交于
Current Makefile.spl passes -R parameter which is not empty and pointing to ./ folder. "./tools/mkimage -T zynqmpimage -R ./"" -d spl/u-boot-spl.bin spl/boot.bin" That's why mkimage is trying to parse ./ file and generate register init which is wrong. Check that passed filename is regular file. If not do not work with it. Signed-off-by: NMichal Simek <michal.simek@xilinx.com>
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由 Mike Looijmans 提交于
The Zynq/ZynqMP boot.bin file contains a region for register initialization data. Filling in proper values in this table can reduce boot time (e.g. about 50ms faster on QSPI boot) and also reduce the size of the SPL binary. The table is a simple text file with register+data on each line. Other lines are simply skipped. The file can be passed to mkimage using the "-R" parameter. It is recommended to add reg init file to board folder. For example: CONFIG_BOOT_INIT_FILE="board/xilinx/zynqmp/xilinx_zynqmp_zcu102/reg.int Signed-off-by: NMike Looijmans <mike.looijmans@topic.nl> Signed-off-by: NMichal Simek <michal.simek@xilinx.com>
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由 Tom Rini 提交于
Signed-off-by: NTom Rini <trini@konsulko.com>
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由 Hans de Goede 提交于
Ian has not had any time for sunxi for some time now and I'm in the same situation now, so I'm stepping down as sunxi custodian and marking the sunxi support as Orphan. Cc: Maxime Ripard <maxime.ripard@free-electrons.com> Cc: Chen-Yu Tsai <wens@csie.org> Cc: Ian Campbell <ijc@hellion.org.uk> Signed-off-by: NHans de Goede <hdegoede@redhat.com> Acked-by: NIan Campbell <ijc@hellion.org.uk>
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- 14 11月, 2016 15 次提交
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由 Stefan Roese 提交于
Compiling the 'bmp' command with DM and having one of the following macros enabled: CONFIG_BMP_16BPP, CONFIG_BMP_24BPP ONFIG_BMP_32BPP generates this error: drivers/video/video_bmp.c: In function ‘video_bmp_display’: drivers/video/video_bmp.c:315:22: error: ‘lcd_line_length’ undeclared (first use in this function) fb -= width * 2 + lcd_line_length; ^ This patch moves to using the correct variable instead and enables the 'bmp' command for DM again. Signed-off-by: NStefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Anatolij Gustschin <agust@denx.de>
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由 Marek Vasut 提交于
If mac-address is changed using "setenv ethaddr ...." command the new mac-adress also must be written into the responsible ethernet driver. This fixes the legacy ethernet handling. Signed-off-by: NMarek Vasut <marex@denx.de> Cc: Hannes Schmelzer <oe5hpm@oevsv.at> Cc: Joe Hershberger <joe.hershberger@ni.com> Cc: Tom Rini <trini@konsulko.com> Reviewed-by: NHannes Schmelzer <oe5hpm@oevsv.at>
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由 Vignesh R 提交于
Fix the divider calculation logic to choose a value so that the resulting baudrate is either equal to or closest possible baudrate less than the requested value. While at that, cleanup ti_spi_set_speed(). Signed-off-by: NVignesh R <vigneshr@ti.com> Reviewed-by: NJagan Teki <jagan@openedev.com>
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由 Vignesh R 提交于
Update the spi-max-frequency property of m25p80 flash slave to match that of TI QSPI controller node, so that QSPI operations happen at maximum supported frequency of 76.8MHz. Signed-off-by: NVignesh R <vigneshr@ti.com> Reviewed-by: NJagan Teki <jteki@openedev.com>
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由 Lokesh Vutla 提交于
Only a certain set of PLLM/D values are recommended to configure the DDR at the required speeds for a given clock input frequency. Updating these values as specified in Data Sheet[1] Table 5-18 [1] http://www.ti.com/lit/ds/symlink/66ak2g02.pdfSigned-off-by: NLokesh Vutla <lokeshvutla@ti.com> Reviewed-by: NTom Rini <trini@konsulko.com>
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由 Lokesh Vutla 提交于
Update the PLL initialization sequence to avoid glitches while programming. User guide for the same is available at[1]. [1] http://www.ti.com/lit/ug/sprugv2h/sprugv2h.pdfSigned-off-by: NLokesh Vutla <lokeshvutla@ti.com> Reviewed-by: NTom Rini <trini@konsulko.com>
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由 Keerthy 提交于
While we setup the mmu initially we mark set_section_dcache with DCACHE_OFF flag. In case of non-LPAE mode the DCACHE_OFF macro is rightly defined with TTB_SECT_XN_MASK set so as to mark all the 4GB XN. In case of LPAE mode XN(Execute-never) bit is not set with DCACHE_OFF. Hence XN bit is not set by default for DCACHE_OFF which keeps all the regions execute okay and this leads to random speculative fetches in random memory regions which was eventually caught by kernel omap-l3-noc driver. Fix this to mark the regions as XN by default. Signed-off-by: NKeerthy <j-keerthy@ti.com> Reviewed-by: NAlexander Graf <agraf@suse.de> Reviewed-by: NTom Rini <trini@konsulko.com>
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由 Keerthy 提交于
Printing the option value in hex makes it more comprehensible. Signed-off-by: NKeerthy <j-keerthy@ti.com> Reviewed-by: NTom Rini <trini@konsulko.com>
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由 Diego Dorta 提交于
Add a README file to help users getting started with the board. Signed-off-by: NDiego Dorta <diego.dorta@nxp.com> Reviewed-by: NFabio Estevam <fabio.estevam@nxp.com> Reviewed-by: NPeng Fan <peng.fan@nxp.com> Reviewed-by: NJagan Teki <jagan@openedev.com>
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由 Fabien Parent 提交于
If the MAC address specified on the EEPROM is invalid (multicast or zero address), then u-boot fails to boot. Having a bad MAC address in the EEPROM should not prevent the system from booting. This commit changes the error path to just print an error messages in case of bad MAC address. Signed-off-by: NFabien Parent <fparent@baylibre.com> Reviewed-by: NTom Rini <trini@konsulko.com>
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由 Alex G 提交于
In most cases, the SPL and u-boot.img will be on the same boot media. Since the SPL was loaded by the boot rom, the pinmux will already have been configured for this media. This, the board will still be able to boot successfully, or at least reach the u-boot console, where more recovery options are available. I've encountered this on a beaglebone black with a corrupted EEPROM. Removing this check allowed the board to boot successfully. I've also seen this on EVM-based boards with an unprogrammed EEPROM. On those boards, for some reason there were no UART messages. This made it look as if the SOC was dead. Remove the hang(), as it is not a fatal error. Also reformat the error message to be clearer as to the cause. The original message made it appear as if the wrong binary was being loaded. Signed-off-by: NAlexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-by: NTom Rini <trini@konsulko.com>
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由 Ladislav Michl 提交于
Tested on IGEPv2 with Micron MT29F4G16ABBDA3W and Hynix H27S4G6F2DKA-BM Signed-off-by: NLadislav Michl <ladis@linux-mips.org> Reviewed-by: NJavier Martinez Canillas <javier@samsung.com> Tested-by: NJavier Martinez Canillas <javier@samsung.com>
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由 Ladislav Michl 提交于
Defconfigs should remain the same except CONFIG_SYS_EXTRA_OPTIONS. Drop NAND specific defconfig as flash type is runtime detected. Signed-off-by: NLadislav Michl <ladis@linux-mips.org> Reviewed-by: NJavier Martinez Canillas <javier@samsung.com>
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由 Ladislav Michl 提交于
As a single U-Boot binary can now run on various board modifications, drop CONFIG_DISPLAY_BOARDINFO as it prints flash memory information too early to give us chance to easily detect it. Also saves few bytes as a bonus. Signed-off-by: NLadislav Michl <ladis@linux-mips.org> Reviewed-by: NJavier Martinez Canillas <javier@samsung.com> Tested-by: NJavier Martinez Canillas <javier@samsung.com>
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由 Andre Przywara 提交于
Commit fed329ae ("tools: add mksunxiboot to tools-all target") added mksunxiboot to the tools-all target, but used the CONFIG_SUNXI symbol to enable its build. Now commit aec9a0f1 ("sunxi: Rename CONFIG_SUNXI to CONFIG_ARCH_SUNXI"), merged before that, renamed that symbol, so that the first patch basically gets ineffective. Adjust the symbol name in tools/Makefile to make it build again. Reviewed-by: NHans de Goede <hdegoede@redhat.com> Signed-off-by: NAndre Przywara <andre.przywara@arm.com>
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- 08 11月, 2016 8 次提交
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由 Stephen Warren 提交于
An SMC call is required for all cache-wide operations on Tegra186. This patch implements the two missing hooks now that U-Boot supports them, and fixes the mapping of "hook name" to SMC call code. Signed-off-by: NStephen Warren <swarren@nvidia.com> Signed-off-by: NTom Warren <twarren@nvidia.com>
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由 Stephen Warren 提交于
SoC-specific logic may be required for all forms of cache-wide operations; invalidate and flush of both dcache and icache (note that only 3 of the 4 possible combinations make sense, since the icache never contains dirty lines). This patch adds an optional hook for all implemented cache-wide operations, and renames the one existing hook to better represent exactly which operation it is implementing. A dummy no-op implementation of each hook is provided. Signed-off-by: NStephen Warren <swarren@nvidia.com> Reviewed-by: NSimon Glass <sjg@chromium.org> Signed-off-by: NTom Warren <twarren@nvidia.com>
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由 Stephen Warren 提交于
When performing a cache disable function, code must not access DRAM. That is because when the cache is disabled, it will be bypassed and all loads and stores will be serviced by RAM. This prevents accessing any dirty data in the cache. In turn, this means the stack cannot be used, since that is in RAM. To guarantee that code doesn't use RAM (and in particular the stack) __asm_flush_l3_cache() must be manually implemented in assembly, rather than implemented in C since the compiler won't know not to touch RAM. Signed-off-by: NStephen Warren <swarren@nvidia.com> Signed-off-by: NTom Warren <twarren@nvidia.com>
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由 Stephen Warren 提交于
nvtboot_boot_x0 is a 64-bit variable and hence must be 64-bit aligned. So far this has happened by accident! Fix the code so this is guaranteed. This fixes the following build error: ... relocation truncated to fit: R_AARCH64_LDST64_ABS_LO12_NC against symbol `nvtboot_boot_x0' ... Signed-off-by: NStephen Warren <swarren@nvidia.com> Signed-off-by: NTom Warren <twarren@nvidia.com>
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Use random ethernet address if the ethernet address found is invalid, not zero and config for random address is defined. Signed-off-by: NSiva Durga Prasad Paladugu <sivadur@xilinx.com> Signed-off-by: NMichal Simek <michal.simek@xilinx.com> Acked-by: NJoe Hershberger <joe.hershberger@ni.com>
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由 Chris Packham 提交于
Commit 5a49f174 ("net: mii: Use spatch to update miiphy_register") updated the mvgbe implementation of smi_reg_read/smi_reg_write. Prior to that change mvgbe_phy_read and mvgbe_phy_write where used as wrappers to satisfy the phylib APIs. Because these functions weren't updated in that commit build errors where triggered when CONFIG_PHYLIB was enabled. Fix these build errors by removing mvgbe_phy_read and mvgbe_phy_write and using smi_reg_read/smi_reg_write directly. Signed-off-by: NChris Packham <judge.packham@gmail.com> Acked-by: NJoe Hershberger <joe.hershberger@ni.com>
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